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| TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H2 Series TMP94C241C Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of X1) with IDLE or STOP mode (RUN is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP94C241C CMOS 32-bit Microcontroller TMP94C241CF 1. Outline and Device Characteristics TMP94C241C is high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. TMP94C241C is a microcontroller which has a high-performance CPU (900/H2 CPU) and various built-in I/Os. And TMP94C241C is enhanced memory interface functions. TMP94C241CF is housed in an 160-pin mini flat package. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H2 CPU) * * * * Compatible with TLCS-900, 900/L, 900/L1, 900/H's instruction code 16 Mbytes of linear address space General-purpose registers and register banks Micro DMA: 8 channels (250 ns/4 bytes at 20 MHz) (2) Minimum instruction execution time: 50 ns (at 20 MHz) (3) Internal memory Internal RAM: 2 Kbytes (can use for code section) Internal ROM: None (4) External memory expansion * * * Expandable up to 16 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus Chip select output: 6 channels Direct interface (supported 8-/16-/32-bit external data bus) (7) 8-bit timer: 4 channels (5) Memory controller (6) DRAM controller: 2 channels 030619EBP1 * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 94C241C-1 2005-05-10 TMP94C241C (8) 16-bit timer: 4 channels (9) Serial interface: 2 channels (10) 10-bit AD converter: 8 channels (with sample hold circuit) (11) 8-bit DA converter: 2 channels (with CMOS-AMP) (12) Watchdog timer (13) Interrupt controller 18 internal interrupts 10 external interrupts (14) I/O port: 64 pins (15) Package: 160-pin QFP (P-QFP160-2828-0.65A) 94C241C-2 2005-05-10 TMP94C241C Figure 1.1 TMP94C241C Block Diagram 94C241C-3 2005-05-10 TMP94C241C 2. 2.1 Pin Assignment and Functions Pin Assignment (Top view) Figure 2.1 Pin Assignment 94C241C-4 2005-05-10 TMP94C241C 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/6) Pin name P00 to P07 D0 to D7 Number of pins 8 (TTL) I/O I/O I/O Port 0: I/O port Data: 0 to 7 for data bus Functions TMP94C241C is external ROM type, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins are put in the high-impedance state. P10 to P17 D8 to D15 8 (TTL) I/O I/O Port 1: I/O port Data: 8 to 15 for data bus If TMP94C241C is external ROM type and is start with 16- or 32-bit data bus, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins are put in the high-impedance state. P20 to P27 D16 to D23 8 (TTL) I/O I/O Port 2: I/O port Data: 16 to 23 for data bus If TMP94C241C is external ROM type and is start with 32-bit data bus, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins are put in the high-impedance state. P30 to P37 D24 to D31 8 (TTL) I/O I/O Port 3: I/O port Data: 24 to 31 for data bus If TMP94C241C is external ROM type and is start with 32-bit data bus, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins are put in the high-impedance state. P40 to P47 A0 to A7 8 I/O Output Port 4: I/O port Address: 0 to 7 for address bus TMP94C241C is external ROM type, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins don't change. P50 to P57 A8 to A15 8 I/O Output Port 5: I/O port Address: 8 to 15 for address bus TMP94C241C is external ROM type, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins don't change. P60 to P67 A16 to A23 8 I/O Output Port 6: I/O port Address: 16 to 23 for address bus TMP94C241C is external ROM type, these pins are initialized to this function. When TMP94C241C doesn't access external memories, these pins don't change. P70 RD 1 Output Output Port 70: Output port (output "high" when initialized) Read: Strobe signal for reading external memory When TMP94C241C doesn't access external memory, doesn't output strobe. TMP94C241C is external ROM type, these pins are initialized to this function. P71 WRLL 1 Output Output Port 71: Output port (output "high" when initialized) Write LL: Strobe signal for writing data on pins D0 to D7 When TMP94C241C doesn't access external memory, doesn't output strobe. 94C241C-5 2005-05-10 TMP94C241C Table 2.2.2 Pin Names and Functions (2/6) 94C241C-6 2005-05-10 TMP94C241C Table 2.2.3 Pin Names and Functions (3/6) 94C241C-7 2005-05-10 TMP94C241C Table 2.2.4 Pin Names and Functions (4/6) 94C241C-8 2005-05-10 TMP94C241C Table 2.2.5 Pin Names and Functions (5/6) F1: F4: 94C241C-9 2005-05-10 TMP94C241C Table 2.2.6 Pin Names and Functions (6/6) (Connect all DVCC pins to +5V.) (Connect all DVSS pins to GND(0V).) 94C241C-10 2005-05-10 TMP94C241C 3. Operation The following is a block-by-block description of the functions and basic operation of TMP94C241C. 3.1 CPU TMP94C241C contains an advanced, high-speed 32-bit CPU (900/H2 CPU). 3.1.1 CPU Outline 900/H2 CPU is high-speed and high-performance CPU based on 900/H CPU. 900/H2 CPU has expanded 32-bit internal and external data bus to process instructions more quickly. Outline of 900/H2 CPU are as follows: 94C241C-11 2005-05-10 TMP94C241C 3.1.2 Reset Operation When resetting the TMP94C241C microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (2 s at 10 MHz). When the reset is accept, the CPU: * Set the program counter (PC) to the reset vector stored at addresses FFFF00H to FFFF02H. PC (7:0) PC (15:8) PC (23:16) * * * Value at address FFFF00H Value at address FFFF01H Value at address FFFF02H Sets the stack pointer (XSP) to 00000000H Sets bits IFF2 to IFF0 of the status register (SR) to 111 (this sets the interrupt level mask register to level 7). Clears bits RFP1 to 0 of the status register (SR) to 00 (this sets the register banks to 0). After reset is released, the CPU begins execution from the instruction at the location specified in the PC. Other than the changes described above, reset does not alter any internal CPU registers. When reset is accepted, processing of the internal I/O, port, and other pins are as follows: * * * Initializes the internal I/O registers as table of "Special Function Register" in section 5. Set ports pins to general-purpose input port mode. Set the WDTOUT pin to "Low". (However, when reset is released, sets to "High".) When external reset is released, built-in clock doubler begins operation and after the stable time (214 external clock cycles: 1.6 ms at 10 MHz) elapse of the circuit, internal reset is released. The operation of memory controller and DRAM controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP94C241C may be spoiled because the control signals are unstable until power supply becomes stable after power on reset. 94C241C-12 2005-05-10 TMP94C241C 3.1.3 Data bus size after reset release The start data bus size is determined depending on the state of a AM1/AM0 pins just after reset release. Then, the external memory is accessed as follows. For the details, refer to section 3.6 "Memory Controller". 3.1.4 Setting of TEST0, TEST1 Connect TEST0, TEST1 pin to "GND" to use. 94C241C-13 2005-05-10 TMP94C241C 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP94C241C. Note 1: Emulator control area is for emulator, it is mapped F00000H to F10000H address. Don't use this area. On emulator WR signal and RD signal are asserted, when this area is accessed. Be careful to use external memory. Note 2: Don't use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Figure 3.2.1 Memory Map 94C241C-14 2005-05-10 TMP94C241C 3.3 Interrupts TLCS-900/H2 interrupts are controlled by the CPU interrupt mask flip-flops 94C241C-15 2005-05-10 TMP94C241C Interrupt processing Micro DMA Software Start Request Interrupt specified by micro DMA start vector? Yes No Clear interrupt request F - F Read interrupt vector V Clear interrupt request F - F General purpose interrupt processing Data transfer by micro DMA PUSH PC PUSH SR SR COUNT COUNT - 1 Micro DMA processing COUNT = 0 No Yes TC interrupt generated clear vector register PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.3.1 Interrupt Processing Flowchart 94C241C-16 2005-05-10 TMP94C241C 3.3.1 General-purpose Interrupt Processing When accepting an interrupt the CPU operates as follows, which is the same as it is in TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt vectors in accordance with the default priority (which is fixed as follows: the smaller the vector value, the higher the priority), then clears the interrupt request. (2) The CPU pushes the program counter (PC) and the status register (SR) to the system stack area (Area indicated by the XSP). (3) The CPU sets a value in the CPU interrupt mask register 94C241C-17 2005-05-10 TMP94C241C Table 3.3.1 TMP94C241C Interrupt Table 94C241C-18 2005-05-10 TMP94C241C 3.3.2 Micro DMA TMP94C241C supports the micro DMA function. For interrupt requests set for micro DMA, micro DMA processing is performed at the highest priority for maskable interrupts, regardless of the set interrupt level. Since the micro DMA has eight channels, it can transfer continuously by the burst specification which is described later. (1) Micro DMA operation When an interrupt request occurs for an interrupt specified by the micro DMA start vector register, micro DMA sends data to the CPU with the highest priority for maskable interrupts, regardless of the interrupt level set for the interrupt. If IFF = 7, micro DMA request is not accept. The micro DMA function has eight channels. This allows micro DMA to be set for up to eight interrupts at the same time. When micro DMA is accepted, the interrupt request F/F for the micro DMA channel is cleared, data are transferred (1 byte, 2 bytes, and 4 bytes) once from the transfer source address to the transfer destination address (the addresses are set in the control register), and the transfer counter is decremented. If the decremented result is 0, the CPU informs a micro DMA transfer end to the interrupt controller. The interrupt controller generates a micro DMA transfer end interrupt (INTTCn). The CPU clears the micro DMA start vector register (DMAnV) 0, disables the next micro DMA startup, and terminates the micro DMA processing. If the decremented result is other than 0, micro DMA processing is terminated without the burst specification which is described later. In this case, the transfer end interrupt (INTTCN) is not generated. When the interrupt source is used only to start micro DMA, the interrupt level must be set to "0". When the interrupt request generates until the interrupt sources are set to the micro DMA start vector, the CPU performs the general-purpose interrupt processing at the interrupt level of 1 to 6. When simultaneously using the same interrupt resource for both the micro DMA and general-purpose interrupts as described above, set the level of the interrupt source used to start micro DMA lower than the levels of all other interrupt sources. Like other maskable interrupts, the priority of the micro DMA transfer end interrupt is determined by the interrupt level and default priority. If multiple-channel micro DMA requests occur at the same time, the priority is determined by the channel numbers, not the interrupt levels. The lower the channel number, the higher the priority. (CH0 (High) to CH2 (Low).) The transfer source and transfer destination addresses are set in 32-bit control registers. However, as only 24-bit addresses are output, the address space available to micro DMA is 16 Mbytes. 94C241C-19 2005-05-10 TMP94C241C Three transfer modes are supported: 1-byte transfer, 2-byte transfer and 4-byte transfer. For each transfer mode, it is possible to specify whether to increment, decrement, or fix source and destination addresses after transfer. These modes facilitate data transfer from I/O to memory, from memory to I/O, and from I/O to I/O. For transfer mode details, see "Transfer Mode Register Details" later in this manual. As a 16-bit transfer counter is used, micro DMA can perform a maximum of 65536 transfers (initializing the counter to 0000H specifies the maximum number of transfers) and the software start (Total 35 interrupt sources) can be used to start micro DMA processing. Figure 3.3.2 shows the micro DMA cycle for transfer destination address INC mode (the same apart from counter mode). (Condition: 0 waits built-in RAM in the transfer address area.) Figure 3.3.2 Micro DMA Cycle Timing States 1, 2: Instruction fetch cycle (Prefetches the next instruction code) State 3: Micro DMA read cycle State 4: Micro DMA write cycle State 5: (The same as in state 1, 2) 94C241C-20 2005-05-10 TMP94C241C (2) Software Start Function In addition to starting the micro DMA function by interrupts, TMP94C241C includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once. At the end of transfer, the bits of the DMAR register which support the end channel are automatically cleared to "0". Writing again to the DMAB register triggers another software start, provided the micro DMA trance counter is set to other than "0". When the burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after startup of the micro DMA. (3) Transfer control register The transfer source address and the transfer destination address are set by the following registers. These registers set data using "LDC cr,r" instruction. 94C241C-21 2005-05-10 TMP94C241C (4) DMA mode register details 94C241C-22 2005-05-10 TMP94C241C 3.3.3 Interrupt Controller Operation Figure 3.3.3 is a block diagram of the interrupt circuit. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each interrupt channel (36 channels in total), an interrupt request flag (flip-flop), an interrupt priority setting register, and a micro DMA start vector register. The interrupt request flag latches interrupt request from the peripherals. The flag is cleared to zero in the following cases: when reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when the micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing "0" to the clear bit in the interrupt priority setting register). The interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD, INTE12). Six interrupt priorities from 1 to 6 are provided. Setting "0" (or "7") disables the interrupt request. The priority of non-maskable interrupts (NMI pin, watchdog timer) is fixed at 7. If interrupt requests with the same level are generated at the same time, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request to accept first. Reading the 3rd bit and the 7th bit in the interrupt priority setting register sees the state of the interrupt request flag and whether there are the interrupt request of each channel. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 94C241C-23 2005-05-10 TMP94C241C Figure 3.3.3 Block Diagram of Interrupt Controller 94C241C-24 2005-05-10 TMP94C241C (1) Interrupt priority setting register 94C241C-25 2005-05-10 TMP94C241C 94C241C-26 2005-05-10 TMP94C241C (2) External interrupt control Note 1: Disable INT0 request before changing INT0 pin mode from level-sense to edge-sense. Setting example: DI LD (IIMC), xxxxxx0xB ; Switches from level to edge. LD (INTCLR), 0AH ; Clears interrupt request flag. EI Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. 94C241C-27 2005-05-10 TMP94C241C Setting of External Interrupt Pin Function (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the micro DMA start vector, which is listed in table 3.3.1, to the INTCLR register. For example, to clear the INT0 interrupt flag, operate the following register after execution of DI instruction. Clears INT0 interrupt request flag INTCLR 0AH (4) Micro DMA start vector register This register assigns micro DMA processing to an interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. 94C241C-28 2005-05-10 TMP94C241C When the micro DMA transfer counter value reaches 0, the micro DMA transfer end interrupt corresponding to the channel is set to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source of the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until the micro DMA transfer is complete. If the micro DMA start vector of this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining) Symbol DMA0V Start Vector DMA 1 DMA1V Start Vector DMA 2 DMA2V Start Vector DMA 3 DMA3V Start Vector DMA 4 DMA4V Start Vector DMA 5 DMA5V Start Vector DMA 6 DMA6V Start Vector DMA 7 DMA7V Start Vector 107h 106h 105h 104h 103h 102h 101h Name DMA 0 Address 100h 7 - - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - 5 4 3 2 1 0 DMA0 Start Vector DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA1 Start Vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W 0 0 0 0 0 0 DMA2 Start Vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 R/W 0 0 0 0 0 0 DMA3 Start Vector DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R/W 0 0 0 0 0 0 DMA4 Start Vector DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0 R/W 0 0 0 0 0 0 DMA5 Start Vector DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R/W 0 0 0 0 0 0 DMA6 Start Vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R/W 0 0 0 0 0 0 DMA7 Start Vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R/W 0 0 0 0 0 0 94C241C-29 2005-05-10 TMP94C241C (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches 0 after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to "1" specifies a burst. 94C241C-30 2005-05-10 TMP94C241C (6) Notes The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0004H and reads the interrupt vector at address FFFF04H. To avoid the above problem, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (ex. "NOP" * 3times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register INT0 level mode INT0 in level mode is not an edge-detect interrupt, so the interrupt request flip-flop function is canceled. The peripheral interrupt request bypasses the S input of the flip-flop, and acts as the Q output. Changing modes from edge to level automatically clears the interrupt request flag. If the CPU enters the interrupt response sequence as a result of setting INT0 from 0 to 1, INT0 must be held at 1 unit the interrupt response sequence is completed. If the INT0 level mode is used to release a halt, INT0 must be held at 1 from the time INT0 changes from 0 to 1, to the time when the halt is released. (Ensure that INT0 does not go back 0 due to noise before the halt is released.) When switching modes from level to edge, any interrupt request flag set in level mode is not cleared. Accordingly, clear the interrupt request flag using the following sequence. DI LD (IIMC), 00H: Switches from level to edge. LD (INTCLR), 0AH: Clears interrupt request flag. NOP: Wait EI execution NOP: NOP: EI INTRX The interrupt request flip-flop can only be cleared by reset or by reading the serial channel receive buffer, not by an instruction. Wait EI execution Wait EI execution Note: The following instructions or pin changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions that switch to level mode after an interrupt request is generated in edge mode. The pin input changes from high to low after an interrupt request is generated in level mode. ("H" "L") INTRX: Instructions that read the receive buffer. 94C241C-31 2005-05-10 TMP94C241C 3.4 Standby Function Executing the HALT instruction sets either RUN, IDLE, or STOP mode depending on the content of WDMOD [1] HALT mode [2] Release from HALT mode Release from HALT mode can trigger an interrupt request or a reset. A combination of the interrupt mask register * Release by reset All HALT modes can be released by a reset. However, when releasing STOP mode, allow sufficient reset time (at least 2 s) for the oscillator to stabilize. When releasing HALT mode by a reset, the internal RAM retains the data prevailing immediately prior to entering the HALT mode. However, other settings are initialized. On execution of the HALT instruction, the device enters standby state in RUN mode. Release halt using INT0. 94C241C-32 2005-05-10 TMP94C241C 94C241C-33 2005-05-10 TMP94C241C (1) RUN mode Figure 3.4.1 is the timing chart for releasing a halt in RUN mode using an interrupt. In RUN mode, the MCU internal system clock does not stop after the HALT instruction is executed. Only CPU instruction execution stops. Therefore, the CPU performs repeated dummy cycles until the halt state is released. In the halt state, interrupt requests are sample on the cycle of the CLK signal. Figure 3.4.1 Timing Chart for Releasing Halt in RUN Mode Using Interrupt 94C241C-34 2005-05-10 TMP94C241C (2) IDLE mode Figure 3.4.2 is the timing chart for releasing a halt in IDLE mode using an interrupt. In IDLE mode, the MCU internal system clock stops. functions. Only the internal oscillator In the halt state, interrupt requests are sampled synchronously to the system clock. The release from the halt state (operation restart), however, is synchronized with the clock. In IDLE mode, interrupt requests other than external interrupts (NMI, INT0) are disabled. Figure 3.4.2 Timing Chart for Releasing Halt in IDLE Mode Using Interrupt 94C241C-35 2005-05-10 TMP94C241C (3) STOP mode Figure 3.4.3 is the timing chart for releasing a halt in STOP mode using an interrupt. In STOP mode, all internal circuits stop, including the internal oscillator. Also, in STOP mode, all pins, apart from a few exceptions, are set to high impedance and are disconnected from the internal circuit of the MCU. However, setting WDMOD Figure 3.4.3 Timing Chart for Releasing Halt in STOP Mode Using Interrupt 94C241C-36 2005-05-10 TMP94C241C Table 3.4.1 Pin states in STOP mode 94C241C-37 2005-05-10 TMP94C241C Table 3.4.2 I/O Operation During Halt and Release HALT Mode WDMOD RUN 00 IDLE 10 Halt STOP 01 See Table 3.4.1 Interrupt Mask and Request Level Settings HALT Mode Interrupt Request Level Interrupt Mask RUN IDLE x x x x x x x STOP x x x x x x x *1 Interrupt Request Level *2 < Interrupt Mask RUN - - IDLE - - STOP - - NMI INTWD INT0 INT4 to 9, A, B HALT Release Source Interrupt INTT0 to 3 INTTR4 to 9, A, B INTRXD0, 1 INTTXD0, 1 INTAD * 1 x x x x x x x x x x x x *1 x x x x x x RESET : After a halt is released, interrupt processing begins. (Reset initializes the LSI.) : After a halt is released, processing begins from the next address following the HALT instruction. x: Cannot be used to release a halt. *1: Halt is released after the warm-up time has elapsed. *2: Same as a DI instruction. 94C241C-38 2005-05-10 TMP94C241C 3.5 Functions of Ports TMP94C241C has I/O port pins which are shown in Table 3.5.1. In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.5.1 Port Functions (1/2) 94C241C-39 2005-05-10 TMP94C241C Table 3.5.2 Port Functions (2/2) 94C241C-40 2005-05-10 TMP94C241C 3.5.1 Port 0 (P00 to P07/D0 to D7) Port 0 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P0CR and function register P0FC. In addition to functioning as a general-purpose I/O port, port 0 can also function as data bus (D0 to D7). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 0 to the following function pins: Figure 3.5.1 Port 0 Table 3.5.3 Port 0 Registers Note: Read-modify-write is prohibited for P0CR, P0FC registers. 94C241C-41 2005-05-10 TMP94C241C 3.5.2 Port 1 (P10 to P17/D8 to D15) Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port 1 can also function as data bus (D8 to D15). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins: Figure 3.5.2 Port 1 Table 3.5.4 Port 1 Registers Note: Read-modify-write is prohibited for P1CR, P1FC registers. 94C241C-42 2005-05-10 TMP94C241C 3.5.3 Port 2 (P20 to P27/D16 to D23) Port 2 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function as data bus (D16 to D23). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 2 to the following function pins: Figure 3.5.3 Port 2 Table 3.5.5 Port 2 Registers Note: Read-modify-write is prohibited for P2CR, P2FC registers. 94C241C-43 2005-05-10 TMP94C241C 3.5.4 Port 3 (P30 to P37/D24 to D31) Port 3 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O port, port 3 can also function as data bus (D24 to D31). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 3 to the following function pins: Figure 3.5.4 Port 3 Table 3.5.6 Port 3 Registers Note: Read-modify-write is prohibited for P3CR, P3FC registers. 94C241C-44 2005-05-10 TMP94C241C 3.5.5 Port 4 (P40 to P47/A0 to A7) Port 4 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC. In addition to functioning as a general-purpose I/O port, port 4 can also function as data bus (A0 to A7). When accessing internal memory and internal I/O, these pins retain the addresses of the previous bus cycle. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins: Figure 3.5.5 Port 4 Table 3.5.7 Port 4 Registers Note: Read-modify-write is prohibited for P4CR, P4FC registers. 94C241C-45 2005-05-10 TMP94C241C 3.5.6 Port 5 (P50 to P57/A8 to A15) Port 5 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC. In addition to functioning as a general-purpose I/O port, port 5 can also function as data bus (A8 to A15). When accessing internal memory and internal I/O, these pins retain the addresses of the previous bus cycle. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins: Figure 3.5.6 Port 5 Table 3.5.8 Port 5 Registers Note: Read-modify-write is prohibited for P5CR, P5FC registers. 94C241C-46 2005-05-10 TMP94C241C 3.5.7 Port 6 (P60 to P67/A16 to A23) Port 6 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port 6 can also function as data bus (A16 to A23). When accessing internal memory and internal I/O, these pins retain the addresses of the previous bus cycle. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 6 to the following function pins: Figure 3.5.7 Port 6 Table 3.5.9 Port 6 Registers Note: Read-modify-write is prohibited for P6CR, P6FC registers. 94C241C-47 2005-05-10 TMP94C241C 3.5.8 Port 7 (P70 to P76) Port 7 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, port 7 can also function as read/write strobe signals to connect with an external memory and control signals to release bus. A reset initializes P71 to P74 and P76 pins to output port mode, and P75 pin to input port mode. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 70 to the following function pins: Figure 3.5.8 Port 7 (P70 to P74) 94C241C-48 2005-05-10 TMP94C241C Figure 3.5.9 Port 7 (P75, P76) Table 3.5.10 Port 7 Registers Note: Read-modify-write is prohibited for P7CR, P7FC registers. 94C241C-49 2005-05-10 TMP94C241C 3.5.9 Port 8 (P80 to P86) Port 8 is a 7-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P8CR and function register P8FC. In addition to functioning as a general-purpose I/O port, port 8 can also function as chip selection to connect with an external memory and wait input. A reset initializes P80 to P85 pins to output port mode, and P86 pin to input port mode. Figure 3.5.10 Port 8 94C241C-50 2005-05-10 TMP94C241C Table 3.5.11 Port 8 Registers Note: Read-modify-write is prohibited for P8CR, P8FC registers. 94C241C-51 2005-05-10 TMP94C241C 3.5 3.5.10 Port A (PA0 to PA4) Port A is a 5-bit general-purpose I/O port. In addition to functioning as a general-purpose I/O port, port A can also function as external DRAM (channel 0) connection. A reset initializes port A to output port mode. Figure 3.5.11 Port A Table 3.5.12 Port A Registers Note: Read-modify-write is prohibited for PAFC register. 94C241C-52 2005-05-10 TMP94C241C 3.5.11 Port B (PB0 to PB4) Port B is a 5-bit general-purpose I/O port. In addition to functioning as a general-purpose I/O port, port A can also function as external DRAM (channel 1) connection. A reset initializes port A to output port mode. Figure 3.5.12 Port B Table 3.5.13 Port B Registers Note: Read-modify-write is prohibited for PBFC register. 94C241C-53 2005-05-10 TMP94C241C 3.5.12 Port C (PC0 to PC4) Port C is a 2-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PCCR and function register PCFC. In addition to functioning as a general-purpose I/O port, port C can also function as 8-bit timer or 16-bit timer output. A reset initializes port C to input port mode. PCCR register PCFC register PC register TO1/TO3 TO7/TOB 0 1 S 0 1 S PC0 (TO1/TO7) PC1 (TO3/TOB) Selector S Port read data 1 0 Selector Selector Figure 3.5.13 Port C Table 3.5.14 Port C Registers Note: Read-modify-write is prohibited for PCCR, PCFC registers. 94C241C-54 2005-05-10 TMP94C241C 3.5.13 Port D (PD0 to PD6) Port D is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PDCR and function register PDFC. In addition to functioning as a general-purpose I/O port, port D can also function as 16-bit timer I/O and interrupt input. A reset initializes port D to input port mode. PDCR register PDFC register PD register 0 Timer output S Port read data 1 S PD0 (TO4) PD1 (TI4/INT4) PD2 (TI5/INT5) PD4 (TO6) PD5 (TI6/INT6) PD6 (TI7/INT7) Selector 1 0 Selector Timer interrupt request Figure 3.5.14 Port D Table 3.5.15 Port D Registers Note: Read-modify-write is prohibited for PDCR, PDFC registers. 94C241C-55 2005-05-10 TMP94C241C 3.5.14 Port E (PE0 to PE6) Port E is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PECR and function register PEFC. In addition to functioning as a general-purpose I/O port, port E can also function as 8-bit timer or 16-bit timer output and interrupt input. A reset initializes port E to input port mode. PECR register PEFC register PE register 0 Timer output S Port read data 1 S PE0 (TO8) PE1 (TI8/INT8) PE2 (TI9/INT9) PE4 (TOA) PE5 (TIA/INTA) PE6 (TIB/INTB) Selector 1 0 Selector Timer interrupt request Figure 3.5.15 Port E Table 3.5.16 Port E Registers Note: Read-modify-write is prohibited for PECR, PEFC registers. 94C241C-56 2005-05-10 TMP94C241C 3.5.15 Port F (PF0 to PF6) Port F is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PFCR and function register PFFC. In addition to functioning as a general-purpose I/O port, port F can also function as I/O functions of serial interface. A reset initializes port F to input port mode. Figure 3.5.16 Port F 94C241C-57 2005-05-10 TMP94C241C Table 3.5.17 Port F Registers Note: Read-modify-write is prohibited for PFCR, PFFC registers. 94C241C-58 2005-05-10 TMP94C241C 3.5.16 Port G (PG0 to PG7) Port G is an 8-bit general-purpose input-only port. In addition to functioning as a general-purpose I/O port, port G can also function as I/O functions of AD converter. Figure 3.5.17 Port G Table 3.5.18 Port G Register 94C241C-59 2005-05-10 TMP94C241C 3.5.17 Port H (PH0 to PH4) Port H is a 5-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PHCR and function register PHFC. In addition to functioning as a general-purpose I/O port, port H can also function as terminal count output function of micro DMA and interrupt input function. A reset initializes port H to input port mode. PHCR register PHFC register PH register 0 Terminal count output of micro DMA S Port read data 1 0 Selector 1 S PH0 (TC0) PH1 (TC1) PH2 (TC2) PH3 (TC3) Selector PHCR register PHFC register PH register PH4 (INT0) S Port read data 1 0 Selector Selector INT0 interrupt request S INT0 level/edge mode select signal 1 0 Rising edge detector Figure 3.5.18 Port H 94C241C-60 2005-05-10 TMP94C241C Table 3.5.19 Port H Registers Note: Read-modify-write is prohibited for PHCR, PHFC registers. 3.5.18 Port Z (PZ0 to PZ7) Port Z is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PZCR. A reset initializes port Z to input port mode. Figure 3.5.19 Port Z Table 3.5.20 Port Z Registers Note: Read-modify-write is prohibited for PZCR register. 94C241C-61 2005-05-10 TMP94C241C 3.6 Memory Controller Functions TMP94C241C has a memory controller with a variable 6-block address area that controls as follows. (1) 6-block address area support Specifies a start address and a block size respectively for 6-block address area (block 0 to 5). (2) Connecting memory specification Specifies SRAM, ROM and DRAM as memories to connect with the respective block address areas. DRAM is specified only in block 1 and block 3. When SRAM or ROM is specified, a usual bus cycle is executed. When DRAM is specified, DRAM is effectively accessed with built-in DRAM controller. The page access of ROM is also supported in block 2. For details, see section 3.6.4 "ROM Control". (3) Data bus size selection Whether 8-bit, 16-bit or 32-bit is selected as the data bus size of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in three mode mentioned below. 0 waits, 1 wait, 2 waits, 3 waits, N waits (controls with WAIT pin) (5) DRAM control TMP94C241C has DRAM controller to control refresh and DRAM accessing. This document describes in order of the operation after reset release, basic functions and ROM page mode. Each section explains the operation and the register setting method and the signal timing. The register setting method is mentioned as the lists of registers in the final. Note: The operation of memory controller and DRAM controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP94C241C may be spoiled because the control signals are unstable until power supply becomes stable after power-on reset. 3.6.1 94C241C-62 2005-05-10 TMP94C241C 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. * Control register: BnCSH/BnCSL (n = 0 to 5) Sets the basic functions of the memory controller, that is the connecting memory type, the data bus size, the number of waits to be read and written. Memory start address register: MSARn (n = 0 to 5) Sets a start address in the respective block address areas. Memory address mask register: MAMRn (n = 0 to 5) Sets a block size in the respective block address areas. * * In addition to setting of the above-mentioned registers, it is necessary to set the following registers to control ROM page mode access and DRAM. * * * Page ROM control register: PMEMCR Sets to executed ROM page mode accessing. DRAM control register: DRAMnCRL/DRAMnCRH (n = 0 to 1) Sets DRAM access. DRAM refresh control register: DRAMnREF (n = 0 to 1) Sets DRAM refresh operation. 94C241C-63 2005-05-10 TMP94C241C (2) Operation after reset release The start data bus size is determined depending on the state of AM1/AM0 pins just after reset release. Then, the external memory is accessed as follows. AM1/AM0 pins are valid only just after reset release. In the other cases, the data bus width is set to the value set to BnBUS bit of the control register. After reset, only control register (B2CSH/B2CSL) of the block address area 2 is automatically valid. The data bus width which is specified by AM1/AM0 pins is loaded to the bit to specify the bus width of the control register in the block address area 2. The block address area 2 is set to addresses 000000H to FFFFFFH after reset. After reset release, the block address areas are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). Then the control register (BnCS) is set. Set the enable bit (BnE) of the control register to "1" to enable the setting. Set relevant registers to access ROM page mode and DRAM. 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the data bus width, the connecting memory and the number of waits out of the memory controller's functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas. The memory controller compares between the register value and the address every bus cycles. The address bit which is masked by the memory address mask register (MAMRn) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The set value in the register is compared with the block address area on the bus. If the compared result is a match, the memory controller sets the chip select signal (CSn) to "low". (i) Setting memory start address register The MnS23 to 16 bits of the memory start address register respectively correspond with addresses A23 to A16. The lower start address A15 to A0 are always set to address 0000H. Therefore, the start address of the block address area are set to addresses 000000H to FF0000H every 64 Kbytes. 94C241C-64 2005-05-10 TMP94C241C (ii) Setting memory address mask registers The memory address mask register sets whether an address bit is compared or not. Set the register to "0" to compare, or to "1" not to compare. The address bit to be set is depended on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 5: A22 to A15 The above-mentioned bits are always compared. The block address area size is determined by the compared result. The size to be set depending on the block address areas is as follows. (iii) Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register as follows. MSAR1 Register M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with addresses A23 to A16. A15 to A0 are set to "0". Therefore, setting MSAR1 to the above-mentioned value specifies the start address of the block address area 1 to address 110000H. The start address is set as it is in the other block address areas. 94C241C-65 2005-05-10 TMP94C241C MAMR1 Register M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 set whether addresses A21 to A16 and A8 are compared or not. Set the register to "0" to compare, or to "1" not to compare. M1V15 to M1V9 bits set whether addresses A15 to A9 are compared or not with 1 bit. A23 and A22 are always compared. Setting the above-mentioned compares A23 to A9 with the values set as the start addresses. Therefore, 512 bytes of addresses 110000H to 1101FFH are set as the block address area 1, and compared with the addresses on the bus. If the compared result is a match, the chip select signal CS1 is set to "low". The other block address area sizes are specified like this. A23 and A22 are always compared in the block address area 0. Whether A20 to A8 are compared or not is set to the register. Similarly, A23 is always compared in the block address areas 2 to 5. Whether A22 to A15 are compared or not is set to the register. Note: When the set block address area overlaps with the built-in memory area, or both 2 address areas overlap, the block address areas are processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3 > 4 > 5 Note also that any accessed areas outside the address spaces set by CS0 to CS5 are processed as the CS2 space. Therefore, settings of CS2 apply for the control of wait cycles, data bus width, etc., and the CS2 signal is output. 94C241C-66 2005-05-10 TMP94C241C (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows. BnOM1,BnOM0 bit (BnCSH Register) DRAM is set only in the block address are 1 and 3. When ROM is selected, the page mode is accessed. It is possible to specify only in the block address area 2. (3) Data bus width specification The data bus width is set for every block address areas. The bus size is set by the BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows. BnBUS Bit (BnCSH Register) BnBUS1 BnBUS0 0 0 1 1 0 1 0 1 Function 8-bit bus mode (Default) 16-bit bus mode 32-bit bus mode Reserved This way of changing the data bus size depending on the address being accessed is called "dynamic bus sizing". The part where the data is output to is depended on the data size, the bus width and the start address. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive address, do not execute a access to both memories with one command. 94C241C-67 2005-05-10 TMP94C241C 94C241C-68 2005-05-10 TMP94C241C (4) Wait control The external bus cycle completes a wait of two states at least (100 ns at 20 MHz). Setting the BnWW2 to BnWW0 and BnWR2 to BnWR0 of the control register (BnCSL) specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR. BnWW/BnWR Bit (BnCSL register) Note: When DRAM is specified as a connecting memory, setting should be 3 states (1 wait) or more. In the case of DRAM access, the WAIT pin input mode cannot be used. The bus cycle is completed with the set states. The number of states is selected from 2 states (0 waits) to 5 states (3 waits). (i) Waits number fixed mode (ii) WAIT pin input mode This mode samples the WAIT input pins. It continuously samples the WAIT pin sate and inserts a wait if the pin is active. The bus cycle is minimum 2 states. The bus cycle is completed when the wait signal is non-active ("High" level) at 2 states. The bus cycle extends if the wait signal is active at 2 states and more. BnREC Bit (BnCSH register) * When not inserting a dummy cycle (0 waits) * When inserting a dummy cycle (0 waits) Figure 3.6.1 Read Cycle when Dummy Cycle is Inserted 94C241C-69 2005-05-10 TMP94C241C (5) Basic bus timing * External read/write bus cycle (0 waits) * External read/write bus cycle (1 wait) 94C241C-70 2005-05-10 TMP94C241C * External read/write bus cycle (0 waits at WAIT pin input mode) * External read/write bus cycle (n waits at WAIT pin input mode) 94C241C-71 2005-05-10 TMP94C241C * Example of WAIT input cycle (5 waits) FF0 D Q FF1 D Q FF2 D Q FF3 D Q FF4 D Q WAIT CK RES CK RES CK RES CK RES CK RES CLK CS RD WR 94C241C-72 2005-05-10 TMP94C241C 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set the registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers TMP94C241C supports ROM access of the page mode. The ROM access of the page mode is specified only in the block address area 2. ROM page mode is set by the page ROM control register (PMEMCR). Setting OPGE bit of the PMEMCR register to "1" sets the memory access of the block address area 2 to ROM page mode access. The number of read cycles is set by the OPWR1, OPWR0 bit of the PMEMCR register. OPWR1/OPWR0 Bit (PMEMCR register) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. The page size (the number of bytes) of ROM in the CPU side is set to the PR1 and 0 bit of the PMEMCR register. When data is read out until a border of the set page, the controller completes the page reading operation. The start data of the next page is read in the normal cycle. The following data is set to page read again. PR1/PR0 Bit (PMEMCR register) (2) Signal timing pulse For the signal timing pulse, see "Page ROM Read Cycle" in section 4.3.2. 94C241C-73 2005-05-10 TMP94C241C 3.6.5 List of Registers The memory control registers and the settings are described as follows. addresses of the registers, see "Table of Special Function Registers" in section 5. (1) Control register The control register is a pair of BnCSL and BnCSH. (n is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas. In BnCSH, only B2CSH which is corresponded to the block address area 2 has a different configuration from the others. For the Note: Read-modify-write is prohibited. BnWW [2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 011 = WAIT pin input mode 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 011 = WAIT pin input mode Note: 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access Others = (Reserved) 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access Others = (Reserved) BnWR [2:0] Specifies the number of read waits. When DRAM is specified as a connecting memory, setting should be 3 states (1 wait) or more. In the case of DRAM access, the WAIT pin input mode cannot be used. Note: Read-modify-write is prohibited. B2E Enable bit 0 = No chip select signal output 1 = Chip select signal output (Default) Note: B2M After reset release, only the enable bit B2E of B2CS register is valid ("1"). Block address area specification 0 = Sets the block address area of CS2 to addresses 000000H to FFFFFFH. (Default) 1 = Sets the block address area of CS2 to programmable. Note: After reset release, the block address area 2 is set to addresses 000000H to FFFFFFH. 94C241C-74 2005-05-10 TMP94C241C B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle B2OM [1:0] 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS [1:0] Sets the data bus width 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved) Note: The value of B2BUS bit is set according to the state of AM [1:0] pin after reset release. Note: Read-modify-write is prohibited. BnE Enable bit 0 = No chip select signal output (Default) 1 = Chip select signal BnREC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle BnOM [1:0] Sets the connecting device. 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = DRAM 11 = (Reserved) Note: DRAM is set only by B1CS and B3CS. BnBUS [1:0] Sets data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved) 94C241C-75 2005-05-10 TMP94C241C (2) Block address register A start address and an address area of the block address area are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start addresses similarly regardless of the block address areas. The bit to be set by the memory address mask register is depended on the block address area. MnS [23:16] Sets a start address. Sets the start address of the block address areas. The bit are corresponding to the addresses A23 to A16. M0V [20:8] Enables or masks comparison of the addresses. M0V20 to M0V8 are corresponding to addresses A20 to A8. The bit of M0V14 to M0V9 are corresponding to addresses A14 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. M1V [21:8] Enables or masks comparison of the addresses. M1V20 to M1V8 are corresponding to addresses A21 to A8. The bit of M1V15 to M1V9 are corresponding to addresses A15 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 94C241C-76 2005-05-10 TMP94C241C MnV [22:15] Enables or masks comparison of the addresses. MnV22 to MnV15 are corresponding to addresses A22 to A15. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in the block address area 2. OPGE enable bit 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR [1:0] Specifies the number of waits. 00 = 1 state (n-1-1-1 mode) (n 2) (Default) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. PR [1:0] ROM page size 00 = 64 bytes 01 = 32 bytes 10 = 16 bytes (Default) 11 = 8 bytes 94C241C-77 2005-05-10 TMP94C241C Table 3.6.1 Control Register (1/2) Note: Read-modify-write is prohibited for B0CSL to B4CSL and B0CSH to B4CSH registers. 94C241C-78 2005-05-10 TMP94C241C Table 3.6.2 Control Register (2/2) Note: Read-modify-write is prohibited for B5CSL and B5CSH registers. 94C241C-79 2005-05-10 TMP94C241C 3.6.6 Cautions If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6.2. Figure 3.6.2 Read Signal Delay Read Cycle Example: When using an externally connected Flash E2PROM which uses JEDEC standard commands, note that the toggle bit may not be read out correctly. If the read signal in the cycle immediately preceding the access to the Flash E2PROM does not go high in time, as shown in Figure 3.6.3, an unintended read cycle like the one shown in (b) may occur. Figure 3.6.3 Flash E2PROM Toggle Bit Read Cycle When the toggle bit reverses with this unexpected read cycle, TMP94C241C always reads same value of the toggle bit, and cannot read the toggle bit correctly. To avoid this phenomena, the data polling control is recommended. 94C241C-80 2005-05-10 TMP94C241C 3.7 DRAM controller TMP94C241C has a two-channel DRAM controller. In addition, it controls DRAM access, address multiplexed, refresh, etc., as followings. * Mapping area Block address area 1......... 256 to 4 Mbytes Block address area 3......... 32K to 8 Mbytes * Memory access mode 4CAS (32-bit bus), 2CAS (16-bit bus), 1CAS (8-bit bus) Supports the page mode. * * * * * * * Memory access address length Selects of 8 to 11 bits. Refresh mode CAS-before-RAS refresh mode Refresh interval Programmable (78 to 384 states) Refresh cycle width Programmable (2 to 9 states) Self-refresh Sets the self-refresh mode. Arbitration between refresh and access Refresh is prior to access. Wait is automatically inserted to the access cycle. Operation during bus release While the bus is released, there is a mode to support only DRAM refresh operation. The data bus width and the number of waits to access DRAM are set according to the set value to the control register (B1CSH, B3CSH) in the block address are 1 and 3. This wait setting should be 3 states (1 wait) or more. In the case of DRAM access, the WAIT pin input mode cannot be used. The DRAM control register (DRAM0CRL/H, DRAM1CRL/H) and the DRAM refresh control register (DRAM0REF, DRAM1REF) set the other values. DRAM accessing and refresh are explained with the setting method of the registers. 94C241C-81 2005-05-10 TMP94C241C (1) DRAM access pin The DRAM accessing is performed by the following pins. The functions of the pins are depended on the connected data bus width. The data bus width is set to the control register (B1CSH, B3CSH) in the block address area 1 and 3. Note: The 32-bit bus mode is supported only in the channel 1. (2) DRAM access control The DRAM control register (DRAM0CRL/H, DRAM1CRL/H) sets the DRAM access mode. The following explains the operations of the modes and the setting of the register. (i) Address multiplexing In TMP94C241C, the internal address multiplexer outputs the row/column address. The multiplexed address lines depend on the bus size: 8 bits or 11 bits. * Setting method The MUXWn1 and 0 bits of the DRAM control register specify the multiplexed address width. The value set as follows is valid by setting MUXEn bit to "1". MUXWn 94C241C-82 2005-05-10 TMP94C241C The multiplexed access bus size is depended on the data bus width after the multiplexed address width is set. (ii) Page mode access The DRAM page mode is accessed by setting the PGEn bit of the DRAM control register to "1". In the page mode accessing, it is set to the DRAM control register. * Setting method The number of waits in writing is set to the PnWW1, PnWW0 bits. The number of waits in reading is set to the PnWR1, PnWR0 bits. The setting method is the same as follows. PnWW/PnWR bits (iii) DRAM access signal timing For details of the signal timing pulse, see "DRAM Bus Cycle" in section 4.3.3. 94C241C-83 2005-05-10 TMP94C241C (3) DRAM refresh controller TMP94C241C support three refresh controls as followings. * * * CAS-before-RAS interval refresh CAS-before-RAS self-refresh Dummy refresh The DRAM refresh control register (DRAM0REF, DRAM1REF) and the SRFC bit of the DRAM control register control the DRAM refresh operation. The followings explain the setting method and the operations. (i) CAS-before-RAS interval refresh In the CAS-before-RAS interval refresh mode, the RAS and CAS signals which are necessary for DRAM refresh are created according to the refresh interval and the refresh cycle width. * Execution procedure Setting the RCn bit of the DRAM refresh control register (DRAM0REF, DRAM1REF) to "1" inserts the refresh cycle. The refresh cycle width is set to RWn2 to RWn0 bit, and the refresh cycle insertion interval is set to RSn2 to RSn0 bit. When using DRAM, set to at least three cycles. The RWn bit is set as follows. RWn 94C241C-84 2005-05-10 TMP94C241C The refresh insertion interval is set in accordance with the setting of the RSn bit. The refresh cycle insertion interval is set in accordance with the frequency of the system clock as follows. RSn * Refresh cycle timing (ii) CAS-before-RAS self-refresh The CAS-before-RAS self-refresh (Hereinafter referred as self-refresh mode) used when the clock supplied is stopped by a HALT instruction while refreshing using the CAS-before-RAS interval refresh mode (Hereinafter referred to as interval mode). (To stop clock supplied by a HALT instruction, the standby function is set in the IDLE mode or the STOP mode.) 94C241C-85 2005-05-10 TMP94C241C * Execution procedure Setting the SFRCn bit of the DRAM control register to "0" during refresh in usual interval mode executes self-refresh. In the self-refresh mode, the RAS and CAS signals maintain their low levels after turning to "low", as it is in the interval mode. When halt is released and the clock is supplied, "1" is set to the SFRCn bit by halt release detector. The self-refresh mode is automatically released. But "1" isn't set in "RUN mode". After the self-refresh mode is released, RAS and CAS signals turn to "high". The usual refresh is executed to return to the interval refresh mode. * Self-refresh cycle timing (iii) Dummy refresh The dummy refresh executes CAS-before-RAS interval refresh successively. The refresh cycle width is fixed to 4 states; the interval, to 6 states. 94C241C-86 2005-05-10 TMP94C241C * Execution procedure Setting the DMn bit of the DRAM refresh control register (DRAM0REF, DRAM1REF) to "1" generates the dummy refresh. Dummy refresh is released by writing "0" to the DMn bit, by enabling DAM access control, or setting the RCn bit of the DRAM refresh control register to "1" and setting to the interval refresh mode. When dummy refresh mode is released by enabling DRAM access control or by setting the RCn bit of the DRAM refresh control register, the DMn bit is not cleared to 0. * Cycle timing (4) Priorities As the DRAM refresh cycle is asynchronous to the CPU operating cycle, the refresh cycle may overlap with DRAM read and write cycles. If an overlap occurs, the DRAM controller gives priority to the cycle that started first. If the refresh cycle and DRAM access request are generated at the same time, the refresh cycle is given priority. In this case, the DRAM controller automatically inserts wait states in the memory access cycle until the refresh cycle completes. (5) Refresh in the bus release mode TMP94C241C has a bus release function. DRAM accessing pins ( RAS , CAS ) include two modes ; either to release mode (set to high impedance) in the same way as other pins, or to non-release mode (output refresh signals). The BRMn bit of DRAM control register sets these modes. BRMn 94C241C-87 2005-05-10 TMP94C241C * DRAM accessing pin release mode When "0" is input to the BRMn bit and the bus release request pin ( BUSRQ ) is set to active, TMP94C241C acknowledges a bus release request. When the current bus cycle completes, TMP94C241C first set the DRAM accessing pins ( RAS , CAS ) to high, then turns the output buffer off to set the pins to high impedance. As the refresh cycle is asynchronous to the access cycle, when a refresh request is generated and has to wait, the refresh cycle is generated and the bus is released. Only one refresh request generated during the bus release is held. The refresh cycle is generated immediately upon return of the bus mastership to TMP94C241C at bus release completion. * DRAM accessing pin non-release mode When "1" is input to the BRMn bit, DRAM accessing pins do not release the bus when a bus release request occurs. The pins continue to operate but support refresh cycles only. In DRAM accessing pin non-release mode, the bus release timing is not affected by refresh requests. (6) List of registers The registers to control DRAM controller and the settings are described as follows. For the addresses of the registers, see "Table of Special Function Registers" in section 5. DRAM can be set to the connecting memory only in the block address area 1 and 3. DRAM0CRL, DRAM0CRH and DRAM0REF control DRAM (Channel 0) in the block address area 1. DRAM1CRL, DRAM1CRH and DRAM1REF control DRMA (Channel 1) in the block address area 3. 94C241C-88 2005-05-10 TMP94C241C * SFRC0/1 self-refresh control 0 = Self-refresh 1 = No self-refresh * BRM0/1 bus release mode control 0 = Also releases DRAM pin in bus release mode 1 = Does not release DRAM pin in bus release mode. Supports only refresh. * MUXE0/1 address multiplex 0 = Disable 1 = Enable (Make this setting when using DRAM.) * MUXW0/1 [1:0] multiplex address length control 00 = 8 bits 01 = 9 bits 10 = 10 bits 11 = 11 bits * MAC0/1 enable bit 0 = No DRAM access control 1 = DRAM access control 94C241C-89 2005-05-10 TMP94C241C * P0/1WW [1:0] specifies the number of DRAM page mode write waits. 00 = (Reserved) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: * Set the number of waits "n" in the corresponding control register (BnCSL). P0/1WR [1:0] specifies the number of DRAM page mode read waits. 00 = (Reserved) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. * PGE0/1 page mode access enable 0 = No page mode access 1 = Page mode access Note: Please set the same value to PGE0 and PGE1. Setting the different value may occur malfunction. * DM0/1 dummy refresh cycle control 0 = No dummy refresh cycle 1 = Dummy refresh cycle 94C241C-90 2005-05-10 TMP94C241C * RS0/1 [2:0] refresh cycle insertion interval 000 = 78 cycles 001 = 154 cycles 010 = 188 cycles 011 = 226 cycles 100 = 246 cycles 101 = 302 cycles 110 = 308 cycles 111 = 384 cycles * RW0/1 [2:0] refresh cycle width 000 = 2 cycles 001 = 3 cycles 010 = 4 cycles 011 = 5 cycles 100 = 6 cycles 101 = 7 cycles 110 = 8 cycles 111 = 9 cycles * RC0/1 enable bit 0 = No refresh cycle 1 = Refresh cycle (7) Register setting examples The following shows an example of setting block address space 1 (CS1) with addresses 100000H to 1FFFFFH (1-Mbyte space), 8-bit data bus width, write 3 states, read 3 states, no dummy cycle for data bus recovery, and 8-bit address multiplex DRAM mode. MSAR1 = 10H MAMR1 = 3FH B1CSL = 22H B1CSH = 88H DRAM0CRL = 8DH The following shows an example of setting block address space 3 (CS3) with addresses 300000H to 3FFFFFH (1-Mbyte space), 16-bit data bus width, write/read 1 wait, page access, and 10-bit address multiplex DRAM mode. MSAR3 = 30H MAMR3 = 1FH B3CSH = 89H DRAM1CRL = 8DH DRAM1CRH = 58H 94C241C-91 2005-05-10 TMP94C241C Table 3.7.1 List of Registers 94C241C-92 2005-05-10 TMP94C241C 3.8 8-Bit Timers TMP94C241C incorporates four 8-bit timers (timers 0 to 3). Each timer can operate independently or be cascaded to form two 16-bit timers. The 8-bit timers have the following four operating modes. * * * * 8-bit interval timer mode (4 channels) 16-bit interval timer mode (2 channels) The above two modes can be combined (for example, two 8-bit timers and one 16-bit timers) 8-bit programmable square wave (PPG: variable cycle, variable duty) output mode (2 channels) 8-bit PWM (pulse width modulation: variable duty at fixed cycle) output mode (2 channels) Figure 3.8.1 is a block diagram for 8-bit timers (timers 0, 1). Timers 2 and 3, have the same circuit configuration as timers 0 and 1. Each interval timer consists of an 8-bit up counter, an 8-bit comparator, and an 8-bit timer register. One timer flip-flop each (TFF1, TFF3) is provided for the timer pairs: timers 0 and 1, timers 2 and 3. Of the input clock sources for interval timers, the T1, T4, T16, and T256 internal clocks are obtained from the 9-bit prescaler shown in Figure 3.8.2. The 8-bit timer operating mode and the timer flip-flops are controlled by six control registers (T01MOD, T23MOD, TFFCR, T8RUN, T16RUN, and TRDC). 94C241C-93 2005-05-10 TMP94C241C TFFCR TFFCR Figure 3.8.1 8-Bit Timer Block Diagram (Timers 0, 1) TFFCR 94C241C-94 2005-05-10 TMP94C241C [1] Prescaler The input to the 9-bit prescaler is the CPU fundamental clock (fc) divided by four (fc/4). The prescaler generates an input clock for the 8-bit timers, the 16-bit timer/event counters, and baud rate generator, for example. The 8-bit timers can use the following four clock signals: T1, T4, T16, and T256. To set the prescaler to count or stop, use timer control register T16RUN Figure 3.8.2 Prescaler 94C241C-95 2005-05-10 TMP94C241C [2] Up counter The up counter is an 8-bit binary counter that counts up using the input clock specified by timer 0 and 1 mode registers T01MOD, T23MOD. The timer 0, 2 input clocks are selected from internal clocks T1, T4, and T16 in accordance with the T01MOD, T23MOD settings. The timer 1, 3 input clocks vary according to the operating mode. When the up counter is set to 16-bit timer mode, timer 0, 2 overflow output is used as an input clock. When the up counter is set to other than 16-bit timer mode, two further settings are available: internal clocks T1, T16, or T256 based on the T01MOD, T23MOD settings, and timer 0, 2 comparator output (match detect). Example: If T01MOD The T01MOD, T23MOD registers also set the operating mode. A reset sets the up counter to 8-bit timer mode. To control the count, stop, and clear functions of each up counter interval timer, use timer control register T8RUN. A reset clears all up counters and stops the timers. [3] Timer registers The timer registers are 8-bit registers for setting interval times. When the setting of timer registers TREG0 to TREG3 matches the up counter value, the comparator match detect signal becomes active. If "00H" is set, the match detect signal is activated when the up counter overflows. Timer registers TREG0, TREG2 have a double-buffer configuration and are paired with a register buffer. TREG0, 2 enable or disable the double-buffer using timer register double-buffer control register TRDC 94C241C-96 2005-05-10 TMP94C241C A reset initializes Figure 3.8.3 Timer Register 0/2/4/6 Configuration Note: The timer register and register buffer are allocated to the same address in memory. When 94C241C-97 2005-05-10 TMP94C241C Figure 3.8.4 Timer 0/1 Mode Register (T01MOD) 94C241C-98 2005-05-10 TMP94C241C Figure 3.8.5 Timer 2/3 Mode Register (T23MOD) 94C241C-99 2005-05-10 TMP94C241C TFF3C1 TFF3C0 TFF3IE TFF3IS TFF1C1 TFF1C0 TFF1IE TFF1IS Note: Read-modify-write is prohibited. Figure 3.8.6 8-Bit Timer Flip-flop Control Register (TFFCR) 94C241C-100 2005-05-10 TMP94C241C Figure 3.8.7 8-Bit Timer Operation Control Register (T8RUN) 94C241C-101 2005-05-10 TMP94C241C Figure 3.8.8 Timer Register Double-Buffer Control Register (TRDC) Figure 3.8.9 16-Bit Timer Operation Control Register (T16RUN) 94C241C-102 2005-05-10 TMP94C241C Note: Read-modify-write is prohibited. Figure 3.8.10 Timer Register [4] Comparator The comparator compares the up counter value with the timer register value. If the values match, the comparator clears the up counter to 0 and generates an interrupt (INTT0 to INTT3). If the timer flip-flop invert is enabled at this time, the comparator inverts the timer flip-flop value. [5] Timer flip-flops (timer F/F) Each interval timer match detect signal (comparator output) inverts the timer flip-flops and outputs the values to timer output pins TO1 (also used as PC0), TO3 (also used as PC1). One timer flip-flop is provided for a timer pair: TFF1 for timer pair 0, 1; TFF3 for pair 2, 3. TFF1 is output to pin TO1, TFF3 to pin TO3. 94C241C-103 2005-05-10 TMP94C241C The following explains the operation of the 8-bit timers. (1) 8-bit timer mode Four interval timers 0 to 3 can be used independently as 8-bit interval timers. As all the timers operate the same, the following describes timer 1 only. [1] Generating a fixed-interval interrupt When using timer 1 to generate a timer 1 interrupt (INTT1) for each fixed interval, first halt timer 1, then set the operating mode, input clock, and interval in T01MOD and TREG1. Next, enable INTT1, and start timer 1 counting. Example: If a timer 1 interrupt is required every 40 s at fc = 20 MHz, set the registers in the following order: For input clock selection, see the following table. Table 3.8.1 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer 94C241C-104 2005-05-10 TMP94C241C [2] Generating a square wave with a 50%-duty cycle Invert the timer flip-flop at fixed intervals and output the timer flip-flop values to the timer output pin (TO1). Example: To output a square wave from pin TO1 with an interval of 2.4 s at fc = 20 MHz, set the registers in the following order. Use either timer 0 or 1. The example shows the register settings for timer 1. Figure 3.8.11 Square Wave (50% duty) Output Timing Chart 94C241C-105 2005-05-10 TMP94C241C [3] Setting timer 1 to count up at timer 0 match output Set 8-bit timer mode and set the timer 1 input clock to timer 0 comparator output. Figure 3.8.12 Timer 1 Count-up due to Matching Output of Timer 0 [4] Output invert by software The timer flip-flop (timer F/F) value can be inverted independently of timer operation. For example, writing "00" to TFFCR 94C241C-106 2005-05-10 TMP94C241C When setting 16-bit timer mode, the input clock for timer 1 is provided by the overflow output of timer 0, irrespective of the clock control register TCLK setting. Table 3.8.2 Selection of 16-Bit Timer (Interrupt) Interval and Input Clock To set the timer interrupt interval, set the lower 8 bits in timer register TREG0 and the upper 8 bits in TREG1. Be sure to set TREG0 first (as entering data in TREG0 temporarily disables the compare, while entering data in TREG1 starts the compare). Setting Example: To generate interrupt INTT1 every 0.4 s at fc = 20 MHz, set the following values in timer registers TREG0 and TREG1: Using T16 ( = 6.4 s at 20 MHz) as a timer input clock, 0.4 s / 6.4 s = 62500 = F424H Therefore, set TREG1 to F4H, and TREG0 to 24H. A match between up counter UC0 and TREG0 triggers the timer 0 comparator to generate a match detect signal, but does not clear up counter UC0. No interrupt INTT0 is generated. A match between up counter UC1 and TREG1 at comparator timing triggers the timer 1 comparator to generate a match detect signal. When comparator match detect signals for both timer 0 and timer 1 are generated, up counter 0 and up counter 1 are cleared to 0 and interrupt INTT1 only is generated. When invert is enabled, the value of timer flip-flop TFF1 is inverted. 94C241C-107 2005-05-10 TMP94C241C Example: When TREG1 = 04H, and TREG0 = 80H: Figure 3.8.13 Timer Output for 16-Bit Timer Mode (3) 8-bit programmable pulse generation output mode Timers 0, 2 can output variable frequencies and square waves (pulses) with variable duty. The output pulse can be set to either active low or active high. Timers 1, 3 cannot be used in this mode. Timer 0 outputs from pin TO1 (also used as PC0), timer 2 outputs from pin TO3 (also used as PC1). As timers 0, 2 operate the same, the following describes timer 0 only. 94C241C-108 2005-05-10 TMP94C241C Figure 3.8.14 8-Bit PPG Output Mode Block Diagram Enabling the TREG0 double-buffer in this mode shifts the register buffer value to TREG0 when TREG1 matches UC0. Using the double-buffer facilitates output of waveforms with a low duty ratio (when changing the duty). Register Buffer Operation 94C241C-109 2005-05-10 TMP94C241C Example: Output a 1/4-duty 62.5 kHz-pulse (at fc = 20 MHz) * Determine the set value in the timer register. Setting the frequency to 62.5 kHz generates a square wave with a cycle of t = 1/62.5 kHz = 16 s. Using T1 = 0.4 s (at fc = 20 MHz) results in: 16 s / 0.4 s = 40 Accordingly, set timer register 1 (TREG1) to TREG1 = 40 = 28H. Next, set the duty to 1/4 as follows: t x 1/4 = 16 s x 1/4 = 4 s Accordingly, set timer register 0 (TREG0) to TREG0 = 10 = 0AH. Note: X ; Don't care - ; No change 94C241C-110 2005-05-10 TMP94C241C (4) 8-bit pulse width modulation (PWM) output mode Only timers 0, 2 support this mode, which allows up to two pulse width modulation outputs with 8-bit resolution. For timer 0, PWM is output to pin TO1 (also used as PC0). For timer 2 PWM is output to pin TO3 (also used as PC1). Timers 1, 3 can be used as 8-bit timers. As timers 0, 2 operate the same, the following describes timer 0 only. Timer output is inverted when the up counter UC0 setting and the timer register TREG setting match, or when 2n - 1 (T01MOD specifies one of n = 6, n = 7, or n = 8) counter overflow occurs. The up counter UC0 is cleared by the 2n - 1 counter overflow. In 8-bit PWM output mode, the following conditions must be satisfied: (Timer register setting) < (2n - 1 counter overflow setting) (Timer register setting) 0 Match between TREG0 and up counter 0 2 -1 overflow (interrupt INTT0) TO1 tPWM (PWM interval) n 94C241C-111 2005-05-10 TMP94C241C Figure 3.8.15 8-Bit PWM Output Mode Block Diagram Enabling the TREG0 double-buffer in this mode shifts the register buffer value to TREG0 when 2n - 1 overflow is detected. Using the double-buffer facilitates output of waveforms with a low duty ratio (when changing the duty). Register Buffer Operation 94C241C-112 2005-05-10 TMP94C241C Example: Output the following PWM waveform to pin TO1 using timer 0 for fc = 20 MHz: To realize a PWM interval of 50.8 s using T1 = 0.4 s (at fc = 20 MHz) 50.8 s / 0.4 s = 127 = 2n - 1 Accordingly, set n = 7. As the low-level interval is 36.0 s, at T1 = 0.4 s, set 36.0 s / 0.4 s = 90 = 5AH in TREG0 Table 3.8.3 Setting PWM Interval and 2n - 1 Counter 94C241C-113 2005-05-10 TMP94C241C (5) Table 3.8.4 shows the settings for all 8-bit timer modes. Table 3.8.4 Setting Register for All Timer Modes 94C241C-114 2005-05-10 TMP94C241C 3.9 16-Bit Timers TMP94C241C incorporates four multi-function 16-bit timer/event counters (timers 4, 6, 8, and A). * * * * * * 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) output mode Frequency measurement mode Pulse width modulation (PWM) mode Time differential measurement mode The timer/event counters have a 16-bit up counter, two 16-bit timer registers (one with a double-buffer configuration), two 16-bit capture registers, two comparators, capture input control, and timer flip-flops and accompanying F/F control circuit. The timer/event counter is controlled by four control registers: T4MOD/T6MOD/ T8MOD/TAMOD, T4FFCR/T6FFCR/T8FFCR/TAFFCR, T16RUN and T16CR. Figure 3.9.1 to Figure 3.9.4 is a block diagram of a 16-bit timer/event counter (timer 4, 6, 8, A). 94C241C-115 2005-05-10 TMP94C241C Figure 3.9.1 16-Bit Timer Block Diagram (Timer 4) 94C241C-116 2005-05-10 TMP94C241C Figure 3.9.2 16-Bit Timer Block Diagram (Timer 6) 94C241C-117 2005-05-10 TMP94C241C Figure 3.9.3 16-Bit Timer Block Diagram (Timer 8) 94C241C-118 2005-05-10 TMP94C241C Figure 3.9.4 16-Bit Timer Block Diagram (Timer A) 94C241C-119 2005-05-10 TMP94C241C 7 T4MOD (0098H) Bit symbol Read/Write After reset Function - - 6 - - 5 CAP4IN W - 4 CAP45M1 0 R/W 3 CAP45M0 0 2 CLE R/W 0 1: UC4 clear enable 1 T4CLK1 R/W 0 Source clock 00: TI4 01: T1 10: T4 11: T16 0 T4CLK0 0 0: Software Capture timing capture 00: Disable 1: Don't 01: TI4 TI5 care 10: TI4 TI4 11: TFF1 TFF1 Timer 4 input clock 00 01 10 11 External input clock (TI4) Internal clock T1 (8/fc) Internal clock T4 (32/fc) Internal clock T16 (128/fc) Up counter UC4 clear 0 1 Disables up counter clear. Clears by match with TREG5. Timer 4 capture timing Capture control 00 01 Capture disable CAP4 on TI4 rising CAP5 on TI5 rising 10 CAP4 on TI4 rising CAP5 on TI4 falling 11 INT4 generated on TI4 rising INT4 generated on TI4 falling CAP4 on TFF1 rising INT4 CAP5 on TFF1 falling generated on TI4 rising Software capture 0 1 Loads up counter 4 value to CAP4. Disables software capture to CAP4. INT4 control Note: Read-modify-write is prohibited. Figure 3.9.5 16-Bit Timer Mode Control Register (T4MOD) 94C241C-120 2005-05-10 TMP94C241C 7 T4FFCR (0099H) Bit symbol Read/Write After reset Function - - 6 - - 5 CAP5T4 R/W 0 TFF4 invert trigger 0: Disable trigger 1: Enable trigger At loading of up counter value to CAP5 4 CAP4T4 R/W 0 3 EQ5T4 R/W 0 2 EQ4T4 R/W 0 1 TFF4C1 W - 00: Invert TFF4 01: Set TFF4 10: Clear TFF4 0 TFF4C0 At loading of up counter value to CAP4 At match between up counter and TREG5 11: Don't care At match between up counter and TREG4 Timer flip-flop 4 (TFF4) control 00 01 10 11 Inverts TFF4 value (software invert). Sets TFF4 to "1". Clears TFF4 to "0". Don't care Timer flip-flop 4 (TFF4) invert trigger 0 1 Trigger disable (invert disabled) Trigger enable (invert enabled) CAP5T4: When up counter value is loaded to CAP5 CAP4T4: When up counter value is loaded to CAP4 EQ5T4: When up counter and TREG5 match EQ4T4: When up counter and TREG4 match Note: Read-modify-write is prohibited. Figure 3.9.6 16-Bit Timer 4 F/F Control (T4FFCR) 94C241C-121 2005-05-10 TMP94C241C 7 T6MOD (00A8H) Bit symbol Read/Write After reset Function 0 TFF7 invert trigger 0: Disable trigger 1: Enable trigger At loading of up counter value to CAP7 CAP7T7 R/W 6 EQ7T7 0 5 CAP6IN W - 4 CAP67M1 0 R/W 3 CAP67M0 0 2 CLE R/W 0 1: UC6 clear enable 1 T6CLK1 R/W 0 Source clock 00: TI6 01: T1 10: T4 11: T16 0 T6CLK0 0 At match between up counter and TREG7 0: Software Capture timing capture 00: Disable 1: Don't 01: TI6 TI7 care 10: TI6 TI6 11: TFF1 TFF1 Timer 6 input clock 00 01 10 11 External input clock (TI6) Internal clock T1 (8/fc) Internal clock T4 (32/fc) Internal clock T16 (128/fc) Up counter UC6 clear 0 1 Disables up counter clear. Clears by match with TREG7. Timer 6 capture timing Capture control 00 01 Capture disable CAP6 on TI6 rising CAP7 on TI7 rising 10 CAP6 on TI6 rising CAP7 on TI6 falling 11 INT6 generated on TI6 rising INT6 generated on TI6 falling CAP6 on TFF1 rising INT6 CAP7 on TFF1 falling generated on TI6 rising Software capture 0 1 At loading of up counter 6 value to CAP6 Disables software capture to CAP6 INT6 control Invert trigger of timer flip-flop 7 (TFF7) 0 1 Trigger disable (invert disabled) Trigger enable (invert enabled) CAP7T7: When up counter value is loaded to CAP7 EQ7T7: When up counter and TREG7 match Note: Read-modify-write is prohibited. Figure 3.9.7 16-Bit Timer Mode Control Register (T6MOD) 94C241C-122 2005-05-10 TMP94C241C 7 T6FFCR (00A9H) Bit symbol Read/Write After reset Function 0 00: Invert TFF7 01: Set TFF7 10: Clear TFF7 11: Don't care TFF7C1 W 6 TFF7C0 0 5 CAP7T6 R/W 0 TFF6 invert trigger 0: Disable trigger 1: Enable trigger At loading of up counter value to CAP7 4 CAP6T6 R/W 0 3 EQ7T6 R/W 0 2 EQ6T6 R/W 0 1 TFF6C1 W - 00: Invert TFF6 01: Set TFF6 10: Clear TFF6 0 TFF6C0 * Always read as "11". At loading of up counter value to CAP6 At match between up counter and TREG7 11: Don't care At match between up counter and TREG6 Timer flip-flop 6 (TFF6) control 00 01 10 11 Inverts TFF6 value (software invert). Sets TFF6 to "1". Clears TFF6 to "0". Don't care Timer flip-flop 6 (TFF6) invert trigger 0 1 Trigger disable (invert disabled) Trigger enable (invert enabled) CAP7T6: When up counter value is loaded to CAP7 CAP6T6: When up counter value is loaded to CAP6 EQ7T6: When up counter and TREG7 match EQ6T6: When up counter and TREG6 match Timer flip-flop 7 (TFF7) control 00 01 10 11 Inverts TFF7 value (software invert). Sets TFF7 to "1". Clears TFF7 to "0". Don't care Note: Read-modify-write is prohibited. Figure 3.9.8 16-Bit Timer 6 F/F Control (T6FFCR) 94C241C-123 2005-05-10 TMP94C241C 7 T8MOD (00B8H) Bit symbol Read/Write After reset Function - - 6 - - 5 CAP8IN W - 4 CAP89M1 0 R/W 3 CAP89M0 0 2 CLE R/W 0 1: UC8 clear enable 1 T8CLK1 R/W 0 Source clock 00: TI8 01: T1 10: T4 11: T16 0 T8CLK0 0 0: Software Capture timing capture 00: Disable 1: Don't 01: TI8 TI9 care 10: TI8 TI8 11: TFF1 TFF1 Timer 8 input clock 00 01 10 11 External input clock (TI8) Internal clock T1 (8/fc) Internal clock T4 (32/fc) Internal clock T16 (128/fc) Up counter UC8 clear 0 1 Disables up counter clear. Clears by match with TREG9. Timer 8 capture timing Capture control 00 01 Capture disable CAP8 on TI8 rising CAP9 on TI9 rising 10 CAP8 on TI8 rising CAP9 on TI8 falling 11 INT8 generated on TI8 rising INT8 generated on TI8 falling CAP8 on TFF1 rising INT8 CAP9 on TFF1 falling generated on TI8 rising Software capture 0 1 At loading of up counter 8 value to CAP8 Disables software capture to CAP8 INTA control Note: Read-modify-write is prohibited. Figure 3.9.9 16-Bit Timer Mode Control Register (T8MOD) 94C241C-124 2005-05-10 TMP94C241C 7 T8FFCR (00B9H) Bit symbol Read/Write After reset Function - - 6 - - 5 CAP9T8 R/W 0 TFF8 invert trigger 0: Disable trigger 1: Enable trigger At loading of up counter value to CAP9 4 CAP8T8 R/W 0 3 EQ9T8 R/W 0 2 EQ8T8 R/W 0 1 TFF8C1 W - 00: Invert TFF8 01: Set TFF8 10: Clear TFF8 0 TFF8C0 At loading of up counter value to CAP8 At match between up counter and TREG9 11: Don't care At match between up counter and TREG8 Timer flip-flop 8 (TFF8) control 00 01 10 11 Inverts TFF8 value (software invert). Sets TFF8 to "1". Clears TFF8 to "0". Don't care Timer flip-flop 8 (TFF8) invert trigger 0 1 Trigger disable (invert disabled) Trigger enable (invert enabled) CAP9T8: When up counter value is loaded to CAP9 CAP8T8: When up counter value is loaded to CAP8 EQ9T8: When up counter and TREG9 match EQ8T8: When up counter and TREG8 match Note: Read-modify-write is prohibited. Figure 3.9.10 16-Bit 8 F/F Control (T8FFCR) 94C241C-125 2005-05-10 TMP94C241C 7 TAMOD (00C8H) Bit symbol Read/Write After reset Function 0 CAPBTB R/W 6 EQBTB 0 5 CAPAIN W - 4 CAPABM1 0 R/W 3 CAPABM0 0 2 CLE R/W 0 1: UCA clear enable 1 TACLK1 R/W 0 Source clock 00: TIA 01: T1 10: T4 11: T16 0 TACLK0 0 TFFB invert trigger 0: Disable trigger 1: Enable trigger At loading of up counter value to CAPB At match between up counter and TREGB 0: Software Capture timing capture 00: Disable 1: Don't 01: TIA TIB care 10: TIA TIA 11: TFF1 TFF1 Timer A input clock 00 01 10 11 External input clock (TIA) Internal clock T1 (8/fc) Internal clock T4 (32/fc) Internal clock T16 (128/fc) Up counter UCA clear 0 1 Disables up counter clear. Clears by match with TREGB. Timer A capture timing Capture control 00 01 Capture disable CAPA on TIA rising CAPB on TIB rising 10 CAPA on TIA rising CAPB on TIA falling 11 INTA generated on TIA rising INTA generated on TIA falling CAPA on TFF1 rising INTA CAPB on TFF1 falling generated on TIA rising Software capture 0 1 At loading of up counter A value to CAPA Disables software capture to CAPA INTA control Invert trigger of timer flip-flop B (TFFB) 0 1 Trigger disable (invert disabled) Trigger enable (invert enabled) CAPBTB: When up counter value is loaded to CAPB EQBTB: When up counter and TREGB match Note: Read-modify-write is prohibited. Figure 3.9.11 16-Bit Timer Mode Control Register (TAMOD) 94C241C-126 2005-05-10 TMP94C241C 7 TAFFCR (00C9H) Bit symbol Read/Write After reset Function 0 00: Invert TFFB 01: Set TFFB 10: Clear TFFB 11: Don't care TFFBC1 W 6 TFFBC0 0 5 CAPBTA R/W 0 4 CAPATA R/W 0 3 EQBTA R/W 0 2 EAQTA R/W 0 1 TFFAC1 W - 00: Invert TFFA 01: Set TFFA 10: Clear TFFA 0 TFFAC0 TFFA invert trigger 0: Disable trigger 1: Enable trigger At loading of up counter value to CAPB At loading of up counter value to CAPA At match between up counter and TREGB At match between up counter and TREGA 11: Don't care * Always read as "11". Timer flip-flop A (TFFA) control 00 01 10 11 Inverts TFFA value (software invert). Sets TFFA to "1". Clears TFFA to "0". Don't care Timer flip-flop A (TFFA) invert trigger 0 1 Trigger disable (invert disabled) Trigger enable (invert enabled) CAPBTA: When up counter value is loaded to CAPB CAPATA: When up counter value is loaded to CAPA EQBTA: EQATA: When up counter and TREGB match When up counter and TREGA match Timer flip-flop B (TFFB) control 00 01 10 11 Inverts TFFB value (software invert). Sets TFFB to "1". Clears TFFB to "0". Don't care Note: Read-modify-write is prohibited. Figure 3.9.12 16-Bit Timer A F/F Control (TAFFCR) 94C241C-127 2005-05-10 TMP94C241C Figure 3.9.13 16-Bit Timer Operation Control Register (T16RUN) Figure 3.9.14 16-Bit Timer (4, 6, 8, A) Control Register (T16CR) 94C241C-128 2005-05-10 TMP94C241C 3.9 Note: Read-modify-write is prohibited. Figure 3.9.15 Timer Register 94C241C-129 2005-05-10 TMP94C241C Figure 3.9.16 Capture Register 94C241C-130 2005-05-10 TMP94C241C [1] Up counter The up counter is a 16-bit binary counter that counts up using the input clock specified by 16-bit timer mode control registers T4MOD 94C241C-131 2005-05-10 TMP94C241C Timer registers TREG4, TREG6, TREG8, and TREGA have a double-buffer configuration and are paired with a register buffer. Timer registers TREG4/TREG6/TREG8/TREGA enable/disable the double-buffer function using timer control register T16CR 94C241C-132 2005-05-10 TMP94C241C [3] Capture register The capture register is a 16-bit register for latching the up counter value. Data in the capture registers should be read all 16 bits. When reading the capture register, use the 2-byte data load instruction, or the 1-byte data load instruction twice; first to read data from the lower eight bits, then to read data from the upper eight bits. [4] Capture input control The capture input control circuit controls the timing to latch the up counter UC4/UC6/UC8/UCA value to capture registers CAP4, CAP5/CAP6, CAP7/CAP8, CAP9/CAPA, CAPB. Set the capture register latch timing using T4MOD * * * 94C241C-133 2005-05-10 TMP94C241C [5] Comparator A 16-bit comparator compares the up counter UC4/UC6/UC8/UCA value with the value set in the timer register (TREG4, TREG5/TREG6, TREG7/TREG8, TREG9/TREGA, TREGB) to detect a match. On detection of a match, the comparator generates interrupt INTTR4/INTTR5, INTTR6/INTTR7, INTTR8/INTTR9, INTTRA/INTTRB. Only a match with TREG5/TREG7/TREG9/TREGB clears up counter UC4/UC6/UC8/UCA. (Setting T4MOD 94C241C-134 2005-05-10 TMP94C241C (1) 16-bit timer mode Timers 4, 6, 8, and A operate independently. As both timers operate the same, the following describes timer 4 only. Example: Generate fixed-interval interrupts Set an interval time in timer register TREG5 and generate interrupt INTTR5. Note: X ; Don't care - ; No change (2) 16-bit event counter mode Setting external clock TI4/TI6/TI8/TIA as an input clock in 16-bit timer mode results in an event counter. To obtain a counter value, load the counter value into a capture register using "software capture" and read the captured value from the capture register. The counter counts up at the TI4/TI6/TI8/TIA input rising edge. The TI4/TI6/TI8/TIA pin is also used as PD1/INT4, PD5/INT6, PE1/INT8, PE5/INTA. As timers 4, 6, 8, and A operate the same, the following describes timer 4 only. Note: Set the prescaler to RUN when using a 16-bit counter as an event counter. 94C241C-135 2005-05-10 TMP94C241C (3) 16-bit programmable pulse generation (PPG) output mode As timers 4, 6, 8, and A operate the same, the following describes timer 4 only. To enter PPG mode, set the device to invert timer flip-flop TFF4 and output the TFF4 value from the TO4 pin (also used as PD0) at a match between up counter UC4 and the TREG4/TREG5 register value. The following condition must be satisfied: (TREG4 setting ) < (TREG5 setting). Figure 3.9.17 Programmable Pulse Generation (PPG) Output Waveform 94C241C-136 2005-05-10 TMP94C241C Enabling the TREG4 double-buffer in this mode shifts the value of register buffer 4 to TREG4 when TREG5 matches UC4. Using the double-buffer facilitates output of waveforms with a low duty ratio. Figure 3.9.18 Register Buffer Operation The following is a block diagram of this mode. Figure 3.9.19 16-Bit PPG Mode Block Diagram 94C241C-137 2005-05-10 TMP94C241C (4) Capture function application example As timers 4, 6, 8, and A operate the same, the following describes timer 4 only. The following features of the 16-bit timer can be enabled or disabled as required: loading of up counter UC4 value to capture registers CAP4 and CAP5, inversion of timer flip/flop TFF4 on a match detect signal from comparators CP4 and CP5, and outputting of TFF4 to pin TO4. Many functions can be obtained by combining these features with interrupts. For example: [1] [2] [3] [4] One-shot pulse output from the external trigger pulse Frequency measurement Pulse width measurement Time differential measurement [1] One-shot pulse output from external trigger pulse Set up counter UC4 to free-running using internal clock input. Input the external trigger pulse from pin TI4, and load the up counter value to capture register CAP4 on the TI4 input rising edge (set T4MOD Figure 3.9.20 One-shot Pulse Output (with delay) 94C241C-138 2005-05-10 TMP94C241C Setting Example: On pin TI4, output a 2ms one-shot pulse with a 3ms-delay after an external trigger pulse. Main setting Settings at INT4 Settings at INTTR5 Note: X ; Don't care - ; No change If delay time is not required, invert timer flip-flop TFF4 by loading to capture register 4 (CAP4). Set timer register TREG5 to the sum of the one-shot pulse width (p) and the value of CAP4 at interrupt INT4 (c) (c + p). Enable TFF4 invert on match between TREG5 and up counter UC4. On interrupt INTTR5, disable the timer flip-flop TFF4 invert. 94C241C-139 2005-05-10 TMP94C241C Figure 3.9.21 One-shot Pulse Output (No delay) [2] Frequency measurement This mode is used to measure the frequency of the external clock. Input the external clock on pin TI4 and measure its frequency with the 8-bit timers (timers 0:1) and the 16-bit timer/event counter (timer 4). Set the TI4 input as the timer 4 input clock, and load the value of up counter UC4 to capture register CAP4 when timer flip/flop TFF4 of the 8-bit timer (timer 0:1) rises, and to capture register CAP5 when timer flip/flop TFF4 falls. The frequency is determined from the difference between capture registers CAP4 and CAP5 at the 8-bit timer interrupts (INTT0 or INTT1). Figure 3.9.22 Frequency Measurement For example, if TFF1 is set to "1" for 0.5 s by the 8-bit timers, and the difference between CAP4 and CAP5 is 100, the frequency is 100 / 0.5 [s] = 200 [Hz]. 94C241C-140 2005-05-10 TMP94C241C [3] Pulse width measurement This mode is used for measuring the "high" level width of an external pulse. Input the external pulse through pin TI4 and set the 16-bit timer/event counter to free-running count-up using an internal clock. Load the up counter UC4 value into capture register CAP4 and CAP5 on the rising and falling edge respectively of the external pulse. Interrupt INT4 is generated on the falling edge of pin TI4. The pulse width can now be determined according to the difference between CAP4 and CAP5, and the internal clock interval. For example, if the difference between CAP4 and CAP5 is 100 and the internal clock interval is 0.8 s, the pulse width is 100 x 0.8 s = 80 s. Figure 3.9.23 Pulse Width Measurement Note: Only in pulse width measurement mode where T4MOD 94C241C-141 2005-05-10 TMP94C241C Figure 3.9.24 Time Differential Measurement (5) Phase output mode Set the up counter UC4/6/8/A to free-running and output a signal with any phase differential. As timers 4, 6, 8, and A operate the same, the following describes timer 6 only. A match between up counter UC6 and TREG6 or TREG7 inverts TFF6 or TFF7 respectively, and outputs the invert values to TO6 and TO7 respectively. Figure 3.9.25 Phase Output The following table shows the interval (counter overflow time) of the above waveform output. 94C241C-142 2005-05-10 TMP94C241C 3.10 Serial Channel TMP94C241C features two built-in serial input/output channels. The serial channel operating modes are as follows: * I/O interface mode Mode 0: For receiving and transmitting I/O data for I/O extension, and for receiving and transmitting synchronous I/O data signals (SCLK). Mode 1: 7-bit transmit/receive data Mode 2: 8-bit transmit/receive data Mode 3: 9-bit transmit/receive data * Universal asynchronous receiver transmitter (UART) mode Parity bits can be added in modes 1 and 2. Mode 3 has a wake up function to start slave controllers using serially linked master controllers (multi-controller system). Figure 3.10.1 shows the data formats (for one frame) in each mode. Figure 3.10.1 Data Formats 94C241C-143 2005-05-10 TMP94C241C Serial channel buffer registers temporarily hold data to be transmitted or received (full-duplex), allowing independent transmission and reception. Note that in I/O interface mode, the serial clock (SCLK) is shared between reception and transmission (half-duplex). The buffer register for reception features a double-buffer configuration to prevent overrun error; an extra frame holds data until the data are read by the CPU. That is, a receive buffer holds the data already received, while the buffer register receives the next frame of data. By using CTS and RTS (as no RTS pin is provided, a pin in any port must be controlled by software), it is possible to halt data transmission until the CPU reads the data received after each frame (handshake function). In UART mode, a check function prevents data receive operations from starting due to erroneous start bits being generated by noise or other interference on the line. The channel starts receiving data only when the start bit is detected as normal in at least two of three samplings. When the transmit buffer is empty, an INTTX interrupt is generated to request the CPU to supply the next data to transmit. When the receive buffer has data to be read by the CPU, an INTRX interrupt is generated. When an overrun error, parity error, or framing error is detected at data reception, the corresponding flag 3.10.1 Control Registers Each serial channel is controlled by three control registers (SC0CR, SC0MOD, and BR0CR for channel 0). Transmit/receive data are stored in a register in each channel (SC0BUF for channel 0). 94C241C-144 2005-05-10 TMP94C241C Figure 3.10.2 Serial Mode Control Register (SC0MOD, Channel 0) 94C241C-145 2005-05-10 TMP94C241C Note 1: Note 2: SC1CR (D5H) is provided for channel 1. As the error flags are all cleared after reading, when testing with a bit test instruction, test more than just a single bit. Figure 3.10.3 Serial Control Register (SC0CR, Channel 0) 94C241C-146 2005-05-10 TMP94C241C Note 1: Note 2: Note 3: BR1CR (D7H) is provided for channel 1. To use the baud rate generator, set T16RUN Figure 3.10.4 Baud Rate Generator Control Register (BR0CR, Channel 0) Note: Read-modify-write is prohibited. Figure 3.10.5 Serial Transmit/Receive Register (SC0BUF, Channel 0) 94C241C-147 2005-05-10 TMP94C241C Figure 3.10.6 Serial Mode Control Register (SC1MOD, Channel 1) 94C241C-148 2005-05-10 TMP94C241C Figure 3.10.7 Serial Control Register (SC1CR, Channel 1) 94C241C-149 2005-05-10 TMP94C241C Note 1: Note 2: To use the baud rate generator, set T16RUN Figure 3.10.8 Baud Rate Generator Control Register (BR1CR, Channel 1) Note: Read-modify-write is prohibited. Figure 3.10.9 Serial Transmit/Receive Buffer Register (SC1BUF, Channel 1) 94C241C-150 2005-05-10 TMP94C241C Note: Read-modify-write is prohibited. Figure 3.10.10 Port F Function Register (PFFC) 94C241C-151 2005-05-10 TMP94C241C 3.10 3.10.2 Configuration Figure 3.10.11 is a block diagram of serial channel 0. Serial channel 1 has the same circuit configuration. transmit control Figure 3.10.11 Serial Channel 0 Block Diagram 94C241C-152 2005-05-10 TMP94C241C [1] Baud rate generator The baud rate generator is a circuit to generate the transmission clock signals that control the serial channel transmission rate. The baud rate generator input clock is one of T0 (4/fc), T2 (16/fc), T8 (64/fc), or T32 (256/fc) from the 9-bit prescaler that the baud rate generator shares with the timers. Bits 5 and 4 I/O interface mode Baud rate generator input clock Baud rate = /2 Baud rate generator divisor The relationship between the input clock and the source clock (fc) is: T0 = 4/fc T2 = 16/fc T8 = 64/fc T32 = 256/fc Accordingly, with the source clock set to 19.6608 MHz, when T2 (16/fc) is selected as input clock and the divisor is 8, the baud rate in UART mode is: fc/16 Baud rate = / 16 8 = 19.6608 x 106 / 16 / 8 / 16 = 9600 (bps) Table 3.10.1 shows examples of the baud rates in UART mode. In UART mode, the serial channels use 8-bit timer 2 to obtain the baud rate. Table 3.10.2 shows examples of baud rates using timer 2. Moreover, the external clock input can also be used as the serial clock. The baud rate in this case is determined as follows. Baud rate = External clock input / 16 94C241C-153 2005-05-10 TMP94C241C Table 3.10.1 UART Mode Baud Rate Selection (1) (Using baud rate generator) Table 3.10.2 UART Mode Baud Rate Selection (2) (Using timer 2 input clock T1) 94C241C-154 2005-05-10 TMP94C241C [2] Serial clock generator circuit This circuit generates the transmit/receive basic clock. * In I/O Interface mode In SCLK output mode where SC0CR/SC1CR 94C241C-155 2005-05-10 TMP94C241C [5] Receive buffer The receive buffer has a double-buffer configuration to prevent overrun error. Receive buffer 1 (a shift register buffer) stores the data received bit by bit. When the receive buffer contains seven or eight bits of data, the data are transferred to receive buffer 2 (SC0BUF/SC1BUF), generating interrupt INTRX0/INTRX1. The CPU reads only receive buffer 2 (SC0BUF/SC1BUF). Data can be stored in receive buffer 1 even before the CPU reads receive buffer 2. However, receive buffer 2 must be read before all bits of the next data unit are received by buffer 1. Otherwise, an overrun error occurs and the contents of receive buffer 1 are lost, although the contents of receive buffer 2 and SC0CR Figure 3.10.12 Transmission Clock Generation [7] Transmit control section * In I/O interface mode In SCLK output mode where SC0CR/SC1CR 94C241C-156 2005-05-10 TMP94C241C * In universal asynchronous receiver transmitter (UART) mode When the CPU writes data in the transmit buffer, transmission begins from the next rising edge of the TXDCLK, generating transmission shift clock TXDSFT. Handshake Function The serial channels use the CTS pin to transmit data in units of frames, thus preventing an overrun error. Use SC0MOD/SC1MOD Figure 3.10.13 Handshake Function Notes 1: Notes 2: When the CTS signal rises during transmission, transmission of the next data frame halts after transmission of the current data frame is complete. Transmission begins at the first TXDCLK clock falling edge after the CTS signal falls. Figure 3.10.14 CTS (Clear to Send) Signal Timing 94C241C-157 2005-05-10 TMP94C241C [8] Transmit buffer Transmit buffer (SC0BUF/SC1BUF) shifts out and transmits the transmit data written by the CPU, beginning with the least significant bit, using the transmission shift clock (TxDSFT) generated by the transmission control section. When all bits are shifted out, the empty transmit buffer generates interrupt INTTX0/INTTX1. [9] Parity control circuit When serial channel control register SC0CR 94C241C-158 2005-05-10 TMP94C241C [11] Signal generation timing 1) Receive In UART mode Note: In 9-bit and 8-bit + parity mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. Transmit 2) In I/O interface mode Immediately after rise of last SCLK signal (See Figure 3.10.17) Immediately after rise of last SCLK signal (rising mode), immediately after fall in falling mode (See Figure 3.10.18) When received data are transferred to receive buffer 2 (SC0BUF/SC1BUF) (immediately after final SCLK) (See Figure 3.10.19) When received data are transferred to receive buffer 2 (SC0BUF/SC1BUF) (immediately after final SCLK) (See Figure 3.10.20) Transmission interrupt SCLK output mode generation timing SCLK input mode Receive interrupt generation timing SCLK output mode SCLK input mode 94C241C-159 2005-05-10 TMP94C241C 3.10.3 Operation (1) Mode 0 (I/O interface mode) This mode is used to increase the number of I/O pins for transmitting or receiving data to an external shift register or other external destinations. This mode consists of SCLK output mode for outputting a synchronous clock (SCLK), and SCLK input mode for inputting a synchronous clock (SCLK) from an external source. Figure 3.10.15 Example of SCLK Output Mode Connection Figure 3.10.16 Example of SCLK Input Mode Connection 94C241C-160 2005-05-10 TMP94C241C [1] Transmission In SCLK output mode, each time the CPU transmits data to the transmit buffer, eight data bits are output from the TXD0/1 pin, and a synchronous clock signal is output from the SCLK0/1 pin. When all data are output, INTES0 Timing for writing transmit data SCLK output TXD0/1 TXDSFT ITX0C/ITX1C (INTTX0/1 request) Bit0 Bit1 Bit6 Bit7 Figure 3.10.17 Data Transmission in I/O Interface Mode (SCLK output mode) In SCLK input mode, 8-bit data are output from TXD0/1 pin when SCLK input becomes active while data are written in the transmission buffer by CPU. When all data are output, INTES0 Figure 3.10.18 Data Transmission in I/O Interface Mode (SCLK input mode) 94C241C-161 2005-05-10 TMP94C241C [2] Receiving In SCLK output mode, whenever the CPU reads the received data and clears the receive interrupt flag INTES0 Figure 3.10.19 Data Receive in I/O Interface Mode (SCLK output mode) In SCLK input mode, if SCLK is input after the CPU reads the received data and clears the receive interrupt flag INTES0 Figure 3.10.20 Data Receive in I/O Interface Mode (SCLK input mode) Note: To receive data in either SCLK input mode or SCLK output mode, first enable receive (SC0MOD/SC1MOD 94C241C-162 2005-05-10 TMP94C241C (2) Mode 1 (7-bit UART mode) Setting the serial channel mode register SC0MOD bit0 1 2 3 4 5 6 even parity stop start transmission direction (transmission rate: 2400 bps at fc = 19.6608 MHz) Note: X ; Don't care - ; No change (3) Mode 2 (8-bit UART mode) Setting serial channel mode register SC0MOD bit0 1 2 3 4 5 6 7 odd parity stop start transmission direction (transmission rate: 9600 bps at fc = 19.6608 MHz) 94C241C-163 2005-05-10 TMP94C241C Main routine settings: Interrupt routine processing example: Note: X ; Don't care - ; No change (4) Mode 3 (9-bit UART mode) Setting the serial channel mode register SC0MOD Note: Set, in the ODE register, the TXD pin of the slave controller to open drain output mode. Figure 3.10.21 Serial Link with Wakeup Function 94C241C-164 2005-05-10 TMP94C241C Protocol [1] Configure the master controller and all slave controllers to 9-bit UART mode. [2] Set the SC0MOD [4] The slave controllers receive the above data frame. The slave controller whose select code matches the select code in the data frame received clears its WU bit to 0. [5] The master controller transmits data frames with most significant bit (bit 8) [6] The slave controllers not specified (the controllers whose 94C241C-165 2005-05-10 TMP94C241C Setting example: When linking two slave controllers serially with the master controller using internal clock 1 as the transmission clock. As serial channels 0 and 1 have the same operation in this mode, the following describes channel 0 only. * Main routine: Setting of master controller INTTX0 interrupt routine: * Main routine: PFCR PFFC INTES0 SC0MOD - - X 0 Setting of slave controller1 - X 1 0 - - 0 1 - - 1 1 - X X 1 - - 1 1 0 1 1 1 0 1 0 0 Sets PF0 as TxD pin (open drain output), and PF1 as RxD pin. Enables INTTX0 and INTRX0. Sets to 9-bit UART mode, sets 1 (fc/2) as transmission clock, and sets Interrupt INTRX0 routine : Acc Then SC0MOD SC0BUF - - - 0 - - - - Clears 94C241C-166 2005-05-10 TMP94C241C 3.11 Analog/Digital Converter TMP94C241C incorporates a high-speed, high-precision 10-bit analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are also used as input-only port G pins and can be also used as input ports. Figure 3.11.1 Block Diagram for DA Converter 94C241C-167 2005-05-10 TMP94C241C Figure 3.11.2 AD Control Register (1/2) 94C241C-168 2005-05-10 TMP94C241C Figure 3.11.3 AD Control Register (2/2) 94C241C-169 2005-05-10 TMP94C241C Note: The result registers are used both as AN0 and AN4, AN1 and AN5, AN2 and AN6, and AN3 and AN7. They are stored in ADREG04, ADREG15, ADREG26, and ADREG37. Figure 3.11.4 AD Conversion Result Register (ADREG04, ADREG15) (1/2) 94C241C-170 2005-05-10 TMP94C241C Figure 3.11.5 AD Conversion Result Register (ADREG26, ADREG37) (2/2) 94C241C-171 2005-05-10 TMP94C241C 3.11.1 Operation (1) Analog reference voltage The high analog reference voltage is applied to the VREFH pin, and the low analog reference voltage is applied to the VREFL pin. The reference voltage between VREFH and VREFL is divided by 1024 (using ladder resistance) and compared with the analog input voltage for AD conversion. The switch between VREFH and VREFL can be turned off by writing 0 to ADMOD2 The pins which are not used as analog input channels can be used as ordinary input port pins for port G. (3) Starting AD conversion AD conversion starts when 1 is written to the AD conversion register ADMOD1 94C241C-172 2005-05-10 TMP94C241C (5) AD conversion speed selection There are four AD conversion speed modes. The selection is made by the ADMOD2 94C241C-173 2005-05-10 TMP94C241C Setting example: [1] When the analog input voltage on the AN3 pin is AD-converted at 160-state speed and the result is transferred to the memory address 0100H by the AD interrupt INTAD routine. Main setting INTAD routine [2] When the analog input voltage of the four pins AN4 to AN7 are AD converted at 320-state speed and the channel is set to scan and repeat mode. Main setting Note: X; Don't care -; No change 94C241C-174 2005-05-10 TMP94C241C 3.12 8-Bit Voltage Output-type DA Converter TMP94C241C incorporates a 2-channel, 8-bit resolution DA converter with the following features. * String resistor method buffer output-type 8-bit resolution DA converter with two internal channels * Registers DAREG0 and DAREG1 to control the analog voltage output Figure 3.12.1 is a block diagram of the DA converter. Figure 3.12.1 DA Converter Block Diagram 94C241C-175 2005-05-10 TMP94C241C Figure 3.12.2 DA Converter Registers 94C241C-176 2005-05-10 TMP94C241C 3.12.1 Operation When DA converter drive register DADRV Note: If the miss operation should occur because the DAOUT1 and DAOUT0 terminals are High-Z, connect both terminals to ground via a 100 k pull-down resistor. 94C241C-177 2005-05-10 TMP94C241C 3.13 Watchdog Timer (Runaway detection timer) TMP94C241C incorporates a watchdog timer for detecting runaways. The watchdog timer (WDT) returns the CPU to its normal state after the watchdog timer detects the start of a CPU malfunction (Runaway) due to noise, for example. When the watchdog timer detects a runaway, it generates a non-maskable interrupt to notify the CPU of the runaway and outputs a "0" signal from the watchdog timer out pin ( WDTOUT ) to notify any peripheral devices of the runaway. 3.13.1 Configuration Figure 3.13.1 is a block diagram of the watchdog timer (WDT). Figure 3.13.1 Watchdog Timer Block Diagram 94C241C-178 2005-05-10 TMP94C241C The watchdog timer is a 22-step binary counter, which uses (2/fc) as the input clock. The WDMOD register selects the output of one of four binary counters: 216/fc, 218/fc, 220/fc, or 222/fc. Overflow from the selected counter generates a watchdog timer interrupt and outputs a signal to the watchdog timer out pin. As a result of watchdog timer overflow, the watchdog timer out pin ( WDTOUT ) outputs "0", which can be used as a reset signal for peripheral devices. Clearing the watchdog timer (writing the clear code (4EH) to the WDCR register) sets the WDTOUT pin to "1". In normal mode, the WDTOUT pin continually outputs "0" until the clear code is written to the WDCR register. Figure 3.13.2 Watchdog Timer Output During Overflow 94C241C-179 2005-05-10 TMP94C241C 3.13.2 Control Registers The watchdog timer (WDT) is controlled by three control registers: WDMOD, WDCR and CLKMOD. (1) Watchdog timer mode register WDMOD [1] Setting watchdog timer detection time * * Enable control Set WDMOD7 94C241C-180 2005-05-10 TMP94C241C (3) Clock mode register CLKMOD This register is used to set the warming up time after the stop mode ends. Writing "0" to the CLKMOD Figure 3.13.3 Watchdog Timer Mode Register 94C241C-181 2005-05-10 TMP94C241C Figure 3.13.4 Watchdog Timer Control Register Note: Read-modify-write is prohibited for CLKMOD register. Figure 3.13.5 CLOCK Mode Register 94C241C-182 2005-05-10 TMP94C241C 3.13.3 Operation After the detection time set by the WDMOD [2] Set the watchdog timer detection time to 218/fc. [3] Disable the watchdog timer. [4] Select IDLE mode. [5] Select STOP mode. (Warm-up time 217/fc) Note: X ; Don't care - ; No change 94C241C-183 2005-05-10 TMP94C241C 3.14 Bus Release Function TMP94C241C has a bus request pin ( BUSRQ , also used as P75) for releasing the bus, and a bus acknowledge pin ( BUSAK , also used as P76). Set these pins using P7CR and P7FC. 3.14.1 Operation When the bus release request pin ( BUSRQ ) is set to active (low), TMP94C241C acknowledges a bus release request. When the operand cycle completes, TMP94C241C first sets the address bus (A23 to A0) and the bus control signals ( RD , WRLL , WRLH , WRHL , WRHH , CS0 to CS5 ) simultaneously to high, sets these signals and the output buffer for the data bus (D31 to D0) to off, and sets the BUSAK pin to low, indicating that the bus is released. When using as input port or output port modes, the bus release is not executed for the port, and the output buffer is not turned off. During bus release, TMP94C241C disables all access to the internal I/O registers, although the internal I/O functions are not affected. As the watchdog timer continues to count up during bus release, when using the bus release function, set the runaway detection time in accordance with the bus release time. When inputting "low" into BUSRQ terminal, continue "low" input until BUSAK terminal outputs "low". If the request is released before BUSAK terminal output "low", a memory controller may malfunction. 94C241C-184 2005-05-10 TMP94C241C 4. 4.1 Electrical Characteristics Maximum Ratings Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Electrical Characteristics Vcc = 5V 10%, TA = -20 to 70C X1 = 8 to 10 MHz (Internal operation = 16 to 20 MHz) Note: Typical value are for Ta = 25C and Vcc = 5 V unless otherwise noted. 94C241C-185 2005-05-10 TMP94C241C 94C241C-186 2005-05-10 TMP94C241C 4.3 AC Electrical Characteristics Basic Bus Cycle (1) Read cycle Vcc = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) 4.3.1 No. Symbol 1 tOSC 2 tCYC 3 tCL 4 tCH 5-1 tAD 5-2 tAD3 6-1 tRD 6-2 tRD3 7-1 tRR 7-2 tRR3 8 tAR 9 tRK 10 tHA 11 tHR 12 tAPR 13 tAPH 14 tTK 15 tKT Parameter OSC period (X1/X2) System Clock Period (= T) CLK Low Width CLK High Width A0 to A23 D0 to D31 Input at 0 waits A0 to A23 D0 to D31 Input at 1 wait RD Fall D0 to D31 Input RD Fall D0 to D31 Input Min 100 50 0.5 x T - 15 0.5 x T - 15 Max 125 62.5 @ 20 MHz@ 16 MHz Unit 100 50 10 10 125 62.5 16 16 75 138 49 111 74 136 11 11 0 0 5 125 15 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.0 x T - 50 3.0 x T - 50 1.5 x T - 45 2.5 x T - 45 1.5 x T - 20 2.5 x T - 20 0.5 x T - 20 0.5 x T - 20 0 0 2.0 x T - 120 2.0 x T 15 5 50 100 30 80 55 105 5 5 0 0 -20 100 15 5 at 0 waits at 1 wait at 0 waits at 1 wait RD Low Width RD Low Width A0 to A23 Valid RD Fall RD Fall CLK Fall A0 to A23 Invalid D0 to D31 Hold RD Rise D0 to D31 Hold A0 to A23 Valid PORT Input A0 to A23 Valid PORT Hold WAIT Set-up Time WAIT Hold Time (2) Write cycle Vcc = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) No. Symbol 1 tOSC 2 tCYC 3 tCL 4 tCH 5-1 tDW 5-2 tDW3 6-1 tWW 6-2 tWW3 7 tAW 8 tWK 9 tWA 10 tWD 11 tAPW 12 tTK 13 tKT 14 tRDO Parameter OSC Period (X1 / X2) System Clock Period (= T) CLK Low Width CLK High Width D0 to D31 Valid WRxx Rise at 0 waits D0 to D31 Valid WRxx Rise at 1 wait WRxx Low Width Min 100 50 0.5 x T - 15 0.5 x T - 15 1.25 x T - 35 2.25 x T - 35 1.25 x T - 30 2.25 x T - 30 0.5 x T - 20 0.5 x T - 20 0.25 x T - 5 0.25 x T - 5 Max 125 62.5 @ 20 MHz@ 16 MHz 100 50 10 10 28 78 33 83 5 5 8 8 125 62.5 16 16 43 106 48 111 11 11 11 11 195 15 5 26 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns at 0 waits at 1 wait WRxx Low Width A0 to A23 Valid WRxx Fall WRxx Fall CLK Fall WRxx Rise A0 to A23 Hold WRxx Rise D0 to D31 Hold A0 to A23 Valid PORT Output WAIT Set-up Time WAIT Hold Time RD Rise D0 to D31 Output 2.0 x T + 70 15 5 0.5 x T - 5 170 15 5 20 AC condition Output: P0 to P3 (D0 to D31), P4 to P6 (A0 to A23), P70 ( RD ), P71 to P74 ( WRxx ) High 2.0 V, Low 0.8 V, CL = 50 pF Others High 2.0 V, Low 0.8 V, CL = 50 pF Input: P0 to P3 (D0 to D31) High 2.4 V, Low 0.45 V Others High 0.8 Vcc, Low 0.2 Vcc 94C241C-187 2005-05-10 TMP94C241C (1) Read cycle (0 Waits) tOSC X1 tCYC tCL CLK tCH tTK WAIT tKT A0 to A23 tAD CS0 to CS5 tHA tAR RD tRK tHR tRR tRD D0 to D31 tAPH Port Input (Note) tAPR Port Input Data Input Note 1: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. Note 2: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 94C241C-188 2005-05-10 TMP94C241C (2) Write cycle (0 waits) tOSC X1 tCYC tCL CLK tTK WAIT tCH tKT A0 to A23 CS0 to CS5 tAW WRxx tWK tWA tWW tDW D0 to D31 tRDO RD tWD Data Output tAPW Port Output (Note) Note 1: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. Note 2: WRxx shows WRLL , WRLH , WRHL , WRHH . Note 3: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 94C241C-189 2005-05-10 TMP94C241C (3) Read cycle (1 wait) (4) Write cycle (1 wait) 94C241C-190 2005-05-10 TMP94C241C 4.3.2 Page ROM Read Cycle (1) 3-2-2-2 mode VCC = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) (2) Page ROM read cycle (3-2-2-2 mode) 94C241C-191 2005-05-10 TMP94C241C 4.3 4.3.3 No. Symbol 1 tCYC 2 tRC 3 tPC 4-1 tRAC 4-2 tRAC4 5 tCAC 6-1 tAA 6-2 tAA2 6-3 tAA4 7 tCPA 8 tOFF 9 tRP 10-1 tRAS 10-2 tRAS4 11 tRSH 12 tRHCP 13-1 tCSH 13-2 tCSH4 14 tCAS 15 tRCD 16 tRAD 17 tCRP 18-1 tCP 18-2 tCP2 19 tASR 20 tRAH 21-1 tASC 21-2 tASC2 22 tCAH 23 tAR 24 tRAL 25 tRCS 26 tRCH 27 tRRH 28 tWCH 29 tWCR 30 tWP 31 tRWL 32 tCWL 33 tDS RAS Cycle Time DRAM Bus Cycle VCC = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) Parameter System Clock Period (= T) Page Mode Cycle Time RAS Access Time RAS Access Time @ 4 Clock Access CAS Access Time Min 50 3.00 x T 2.00 x T Max 62.5 @20 MHz @16 MHz Unit 50 150 100 62.5 188 125 64 127 23 33 80 96 80 0 58 89 152 43 105 89 152 43 30 51 58 16 43 38 16 4 43 43 89 58 85 11 11 43 89 74 74 74 58 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.75 x T - 45 2.75 x T - 45 1.00 x T - 40 1.25 x T - 45 2.00 x T - 45 2.25 x T - 45 2.00 x T - 45 0 1.25 x T - 20 1.75 x T - 20 2.75 x T - 20 1.00 x T - 20 2.00 x T - 20 1.75 x T - 20 2.75 x T - 20 1.00 x T - 20 0.75 x T - 17 0.50 x T + 20 1.25 x T - 20 0.50 x T - 15 1.00 x T - 20 1.25 x T - 40 0.50 x T - 15 0.25 x T - 12 1.00 x T - 20 1.00 x T - 20 1.75 x T - 20 1.25 x T - 20 2.00 x T - 40 0.50 x T - 20 0.50 x T - 20 1.00 x T - 20 1.75 x T - 20 1.50 x T - 20 1.50 x T - 20 1.50 x T - 20 1.50 x T - 30 43 93 10 18 55 68 55 0 43 68 118 30 80 68 118 30 21 45 43 10 30 23 10 1 30 30 68 43 60 5 5 30 68 55 55 55 45 Column Address Access Time Column Address Access Time @ Page Mode Column Address Access Time @ 4 Clock Access CAS Pre-charge Access Time Input Data Hold Time RAS Pre-charge Time RAS Width RAS Width @ 4 Clock Access RAS Hold Time CAS Pre-charge to RAS Hold Time CAS Hold Time CAS Hold Time @ 4 Clock Access CAS Width RAS - CAS Delay Time RAS - Column Address Delay Time CAS - RAS Pre-charge Time CAS Pre-charge Time @ Refresh CAS Pre-charge Time @ Page Mode Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Set-up Time @ Page Mode Column Address Hold Time Column Address Hold Time from RAS Column Address RAS Read Time Read Command Set-up Time Read Command Hold Time from CAS Read Command Hold Time from RAS Write Command Hold Time Write Command Hold Time from RAS Write Command Time Write Command RAS Read Time Write Command CAS Read Time Data Output Set-up Time 94C241C-192 2005-05-10 TMP94C241C AC Condition Output: P0 to P3 (D0 to D31), P4 to P6 (A0 to A23), P70 ( RD ), P71 to P74 ( WRxx ) High 2.0 V, Low 0.8 V, CL = 50 pF Others High 2.0 V, Low 0.8 V, CL = 50 pF Input: P0 to P3 (D0 to D31) High 2.4 V, Low 0.45 V Others High 0.8 Vcc, Low 0.2 Vcc 94C241C-193 2005-05-10 TMP94C241C (1) DRAM read cycle (3 clock access) 94C241C-194 2005-05-10 TMP94C241C (2) DRAM write cycle (3 clock access) 94C241C-195 2005-05-10 TMP94C241C (3) DRAM read cycle (4 clock access) 94C241C-196 2005-05-10 TMP94C241C (4) DRAM write cycle (4 clock access) 94C241C-197 2005-05-10 TMP94C241C (5) DRAM page mode read cycle (3-2-2-2 mode) 94C241C-198 2005-05-10 TMP94C241C (6) DRAM page mode write cycle (3-2-2-2 mode) 94C241C-199 2005-05-10 TMP94C241C (7) DRAM CAS before RAS interval refresh cycle (3 cycle mode) (8) DRAM CAS before RAS self refresh cycle 94C241C-200 2005-05-10 TMP94C241C 4.4 Event Counter (TI4, TI5, TI6, TI7, TI8, TI9, TIA, TIB) 4.5 Serial Channel Timing (1) SCLK input mode (I/O interface mode) (2) SCLK output mode (I/O interface mode) (3) SCLK input mode (UART mode) tSCY SCLK tOSS Output Data TXD 0 tOHS 1 tSRD Input Data RXD Valid Valid tHSR 94C241C-201 2005-05-10 TMP94C241C 4.6 10-Bit AD Conversion Characteristics VCC = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) Symbol VREFH VREFL VAIN IREF (VREFL = 0 V) Parameter Analog reference voltage (High) Analog reference voltage (Low) Analog input voltage range Analog current for analog reference voltage VCC = 5V 10% VCC = 5V 10% VCC = 5V 10% Min VCC - 0.2 V VSS VREFL Typ. VCC VSS Max VCC VSS + 0.2 V VREFH Unit V 0.5 0.02 3.0 1.5 5.0 6 mA A LSB Error (Quantize error of 0.5 LSB not included) Note 1: 1LSB = (VREFH - VREFL)/1024 [V] Note 2: Power supply current Icc from the digital power supply includes the power supply from the AVcc pin. 4.7 8-Bit DA Conversion Characteristics VCC = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) Symbol DAREFH DAREFL Parameter Analog reference voltage (+) Analog reference voltage (-) Total error Output voltage range Settling time Condition Min 4.0 VSS Typ. Max VCC Unit V VSS 2.0 4.0 VSS - 0.5 5 5 LSB V s K RL = 2.4 K RL = 2.4 K RL = 2.4 K, CL = 100 pF VSS + 0.5 DAOUT VCC - 0.5 VSS + 0.5 DAC output mode Output impedance Resistance load 2.4 Note: RL is the resistance load of the DA converter output pin. 4.8 Interrupt Operation 94C241C-202 2005-05-10 TMP94C241C 4.9 Bus Request/Bus Acknowledge Timing Note: The bus will be released after the WAIT request is inactive, when the BUSRQ is set to "low" during "wait" cycle. 94C241C-203 2005-05-10 TMP94C241C 5. Table of Special Function Registers (SFRs) The special function registers (SFRs: Special function registers) include the I/O ports and peripheral control registers allocated to the 1024-byte addresses from 000000H to 0003FFH. (1) Input/output ports (2) Timer (3) Watchdog timer (4) Clock control (5) Serial channels (6) AD converter (7) DA converter (8) Interrupt controller (9) Memory controller (10) DRAM controller Configuration of the table Explanations of symbols R/W : Either read or write is possible R: Only read is possible W: Only write is possible W* : Either read or write is possible (Always read as "1" ) 1* : Always read as "1" No RMW : Prohibit read-modify-write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF etc.) 94C241C-204 2005-05-10 TMP94C241C Table 5.1 I/O Register Address Map 94C241C-205 2005-05-10 TMP94C241C Address TLCS-90 type I/O 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h 13Ch 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h Name WDMOD ADREG04L ADREG26L ADMOD1 DAREG0 Address 111h 115h 119h 11Dh 121h 125h 129h 12Dh 131h 135h 139h 13Dh 141h 145h 149h 14Dh 151h 155h 159h 15Dh 161h 165h Name WDCR ADREG04H ADREG26H ADMOD2 DAREG1 Address 112h 116h 11Ah 11Eh 122h 126h 12Ah 12Eh 132h 136h 13Ah 13Eh 142h 146h 14Ah 14Eh 152h 156h 15Ah 15Eh 162h 166h Name ADREG15L ADREG37L (reserved) DADRV Address 113h 117h 11Bh 11Fh 123h 127h 12Bh 12Fh 133h 137h 13Bh 13Fh 143h 147h 14Bh 14Fh 153h 157h 15Bh 15Fh 163h 167h Name ADREG15H ADREG37H TLCS-900/H2 type 8 bit I/O B0CSL B1CSL B2CSL B3CSL B4CSL B5CSL DRAM0CRL DRAM0REF B0CSH B1CSH B2CSH B3CSH B4CSH B5CSH DRAM0CRH DRAM1REF MAMR0 MAMR1 MAMR2 MAMR3 MAMR4 MAMR5 DRAM1CRL PMEMCR MSAR0 MSAR1 MSAR2 MSAR3 MSAR4 MSAR5 DRAM1CRH Note 1: TLCS-900/H2 type I/Os are always accessed by two clocks (100 ns @ 20 MHz). Note 2: TLCS-90 type I/Os are accessed by five clocks min (250 ns @ 20 MHz) and eight clocks max (400 ns @ 20 MHz). 94C241C-206 2005-05-10 TMP94C241C (1) Input/output ports Port 0 Port 1 Port 2 94C241C-207 2005-05-10 TMP94C241C Port 3 Port 4 Port 5 94C241C-208 2005-05-10 TMP94C241C Port 6 Port 7 Port 8 94C241C-209 2005-05-10 TMP94C241C Port A Port B Port C 94C241C-210 2005-05-10 TMP94C241C Port D Port E Port F 94C241C-211 2005-05-10 TMP94C241C Port G Port H Port Z 94C241C-212 2005-05-10 TMP94C241C (2) Timer 8-Bit Timer 01, 23 (no RMW) 94C241C-213 2005-05-10 TMP94C241C 16-Bit Timer Control 16-Bit Timer 4 (no RMW) (no RMW) 94C241C-214 2005-05-10 TMP94C241C 16-Bit Timer 6 (no RMW) (no RMW) 94C241C-215 2005-05-10 TMP94C241C 16-Bit Timer 8 (no RMW) (no RMW) 94C241C-216 2005-05-10 TMP94C241C 16-Bit Timer A (no RMW) (no RMW) 94C241C-217 2005-05-10 TMP94C241C (3) Watchdog timer (4) Clock control 94C241C-218 2005-05-10 TMP94C241C (5) Serial channels (no RMW) 94C241C-219 2005-05-10 TMP94C241C (6) AD converter 94C241C-220 2005-05-10 TMP94C241C (7) DA converter 94C241C-221 2005-05-10 TMP94C241C (8) Interrupt controller INTE0AD 94C241C-222 2005-05-10 TMP94C241C (no RMW) 94C241C-223 2005-05-10 TMP94C241C (no RMW) 94C241C-224 2005-05-10 TMP94C241C (9) Memory controller 94C241C-225 2005-05-10 TMP94C241C 94C241C-226 2005-05-10 TMP94C241C 94C241C-227 2005-05-10 TMP94C241C (10) DRAM controller 94C241C-228 2005-05-10 TMP94C241C 6. Port Section Equivalent Circuit Diagram * Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC (74HCxx) series. The dedicated signal is described below. STOP : This signal becomes active "1" when the halt mode setting register is set to the STOP mode (WDMOD * The input protection resistance ranges from several tens ohms to several hundreds of ohms. P0 (D0 to D7), P1 (D8 to D15), P2 (D16 to D23), P3 (D24 to D31), P4 (A0 to A7), P5 (A8 to A15), P6 (A16 to A23), P75 ( BUSRQ ), P86 ( WAIT ), PC, PD, PE, PF6 ( CTS1, SCLK1), PF5 (RXD1), PF2 (CTS0, SCLK0), PF1 (RXD0), (PH0 to 3), PZ P76 ( BUSAK ), (P70 to P74), (P80 to P85) 94C241C-229 2005-05-10 TMP94C241C PF0 (TXD0), PF4 (TXD1) VCC Output data P-ch Open drain enable Output enable STOP Input data N-ch I/O Input enable PG (AN0 to 7) PH4 (INT0) 94C241C-230 2005-05-10 TMP94C241C RESET X1, X2 VREFH, VREFL 94C241C-231 2005-05-10 TMP94C241C NMI WDTOUT CLK (AM0 to AM1), (TEST0 to TEST1) 94C241C-232 2005-05-10 TMP94C241C 7. Care Points and Restriction (1) Special expression [1] Explanation of a built-in I/O register: Register symbol 94C241C-233 2005-05-10 TMP94C241C 8. Package Dimensions P-QFP160-2828-0.65A Unit: mm 94C241C-234 2005-05-10 |
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